1/* 2 * relocate - common relocation function for ARM U-Boot 3 * 4 * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <asm-offsets.h> 10#include <config.h> 11#include <linux/linkage.h> 12#ifdef CONFIG_CPU_V7M 13#include <asm/armv7m.h> 14#endif 15 16/* 17 * Default/weak exception vectors relocation routine 18 * 19 * This routine covers the standard ARM cases: normal (0x00000000), 20 * high (0xffff0000) and VBAR. SoCs which do not comply with any of 21 * the standard cases must provide their own, strong, version. 22 */ 23 24 .section .text.relocate_vectors,"ax",%progbits 25 .weak relocate_vectors 26 27ENTRY(relocate_vectors) 28 29#ifdef CONFIG_CPU_V7M 30 /* 31 * On ARMv7-M we only have to write the new vector address 32 * to VTOR register. 33 */ 34 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ 35 ldr r1, =V7M_SCB_BASE 36 str r0, [r1, V7M_SCB_VTOR] 37#else 38#ifdef CONFIG_HAS_VBAR 39 /* 40 * If the ARM processor has the security extensions, 41 * use VBAR to relocate the exception vectors. 42 */ 43 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ 44 mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ 45#else 46 /* 47 * Copy the relocated exception vectors to the 48 * correct address 49 * CP15 c1 V bit gives us the location of the vectors: 50 * 0x00000000 or 0xFFFF0000. 51 */ 52 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ 53 mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */ 54 ands r2, r2, #(1 << 13) 55 ldreq r1, =0x00000000 /* If V=0 */ 56 ldrne r1, =0xFFFF0000 /* If V=1 */ 57 ldmia r0!, {r2-r8,r10} 58 stmia r1!, {r2-r8,r10} 59 ldmia r0!, {r2-r8,r10} 60 stmia r1!, {r2-r8,r10} 61#endif 62#endif 63 bx lr 64 65ENDPROC(relocate_vectors) 66 67/* 68 * void relocate_code(addr_moni) 69 * 70 * This function relocates the monitor code. 71 * 72 * NOTE: 73 * To prevent the code below from containing references with an R_ARM_ABS32 74 * relocation record type, we never refer to linker-defined symbols directly. 75 * Instead, we declare literals which contain their relative location with 76 * respect to relocate_code, and at run time, add relocate_code back to them. 77 */ 78 79ENTRY(relocate_code) 80 ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */ 81 subs r4, r0, r1 /* r4 <- relocation offset */ 82 beq relocate_done /* skip relocation */ 83 ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */ 84 85copy_loop: 86 ldmia r1!, {r10-r11} /* copy from source address [r1] */ 87 stmia r0!, {r10-r11} /* copy to target address [r0] */ 88 cmp r1, r2 /* until source end address [r2] */ 89 blo copy_loop 90 91 /* 92 * fix .rel.dyn relocations 93 */ 94 ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */ 95 ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */ 96fixloop: 97 ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */ 98 and r1, r1, #0xff 99 cmp r1, #23 /* relative fixup? */ 100 bne fixnext 101 102 /* relative fix: increase location by offset */ 103 add r0, r0, r4 104 ldr r1, [r0] 105 add r1, r1, r4 106 str r1, [r0] 107fixnext: 108 cmp r2, r3 109 blo fixloop 110 111relocate_done: 112 113#ifdef __XSCALE__ 114 /* 115 * On xscale, icache must be invalidated and write buffers drained, 116 * even with cache disabled - 4.2.7 of xscale core developer's manual 117 */ 118 mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ 119 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 120#endif 121 122 /* ARMv4- don't know bx lr but the assembler fails to see that */ 123 124#ifdef __ARM_ARCH_4__ 125 mov pc, lr 126#else 127 bx lr 128#endif 129 130ENDPROC(relocate_code) 131