1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * GIC Initialization Routines. 4 * 5 * (C) Copyright 2013 6 * David Feng <fenghua@phytium.com.cn> 7 */ 8 9#include <asm-offsets.h> 10#include <config.h> 11#include <linux/linkage.h> 12#include <asm/gic.h> 13#include <asm/macro.h> 14 15 16/************************************************************************* 17 * 18 * void gic_init_secure(DistributorBase); 19 * 20 * Initialize secure copy of GIC at EL3. 21 * 22 *************************************************************************/ 23ENTRY(gic_init_secure) 24 /* 25 * Initialize Distributor 26 * x0: Distributor Base 27 */ 28#if defined(CONFIG_GICV3) 29 mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */ 30 /* EnableGrp1S | ARE_S | ARE_NS */ 31 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ 32 ldr w9, [x0, GICD_TYPER] 33 and w10, w9, #0x1f /* ITLinesNumber */ 34 cbz w10, 1f /* No SPIs */ 35 add x11, x0, (GICD_IGROUPRn + 4) 36 add x12, x0, (GICD_IGROUPMODRn + 4) 37 mov w9, #~0 380: str w9, [x11], #0x4 39 str wzr, [x12], #0x4 /* Config SPIs as Group1NS */ 40 sub w10, w10, #0x1 41 cbnz w10, 0b 42#elif defined(CONFIG_GICV2) 43 mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */ 44 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ 45 ldr w9, [x0, GICD_TYPER] 46 and w10, w9, #0x1f /* ITLinesNumber */ 47 cbz w10, 1f /* No SPIs */ 48 add x11, x0, GICD_IGROUPRn 49 mov w9, #~0 /* Config SPIs as Grp1 */ 50 str w9, [x11], #0x4 510: str w9, [x11], #0x4 52 sub w10, w10, #0x1 53 cbnz w10, 0b 54 55 ldr x1, =GICC_BASE /* GICC_CTLR */ 56 mov w0, #3 /* EnableGrp0 | EnableGrp1 */ 57 str w0, [x1] 58 59 mov w0, #1 << 7 /* allow NS access to GICC_PMR */ 60 str w0, [x1, #4] /* GICC_PMR */ 61#endif 621: 63 ret 64ENDPROC(gic_init_secure) 65 66 67/************************************************************************* 68 * For Gicv2: 69 * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase); 70 * For Gicv3: 71 * void gic_init_secure_percpu(ReDistributorBase); 72 * 73 * Initialize secure copy of GIC at EL3. 74 * 75 *************************************************************************/ 76ENTRY(gic_init_secure_percpu) 77#if defined(CONFIG_GICV3) 78 /* 79 * Initialize ReDistributor 80 * x0: ReDistributor Base 81 */ 82 mrs x10, mpidr_el1 83 lsr x9, x10, #32 84 bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */ 85 mov x9, x0 861: ldr x11, [x9, GICR_TYPER] 87 lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */ 88 cmp w10, w11 89 b.eq 2f 90 add x9, x9, #(2 << 16) 91 b 1b 92 93 /* x9: ReDistributor Base Address of Current CPU */ 942: mov w10, #~0x2 95 ldr w11, [x9, GICR_WAKER] 96 and w11, w11, w10 /* Clear ProcessorSleep */ 97 str w11, [x9, GICR_WAKER] 98 dsb st 99 isb 1003: ldr w10, [x9, GICR_WAKER] 101 tbnz w10, #2, 3b /* Wait Children be Alive */ 102 103 add x10, x9, #(1 << 16) /* SGI_Base */ 104 mov w11, #~0 105 str w11, [x10, GICR_IGROUPRn] 106 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */ 107 mov w11, #0x1 /* Enable SGI 0 */ 108 str w11, [x10, GICR_ISENABLERn] 109 110 /* Initialize Cpu Interface */ 111 mrs x10, ICC_SRE_EL3 112 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ 113 /* Allow EL2 access to ICC_SRE_EL2 */ 114 msr ICC_SRE_EL3, x10 115 isb 116 117 mrs x10, ICC_SRE_EL2 118 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ 119 /* Allow EL1 access to ICC_SRE_EL1 */ 120 msr ICC_SRE_EL2, x10 121 isb 122 123 mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */ 124 msr ICC_IGRPEN1_EL3, x10 125 isb 126 127 msr ICC_CTLR_EL3, xzr 128 isb 129 130 msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */ 131 isb 132 133 mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */ 134 msr ICC_PMR_EL1, x10 135 isb 136#elif defined(CONFIG_GICV2) 137 /* 138 * Initialize SGIs and PPIs 139 * x0: Distributor Base 140 * x1: Cpu Interface Base 141 */ 142 mov w9, #~0 /* Config SGIs and PPIs as Grp1 */ 143 str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */ 144 mov w9, #0x1 /* Enable SGI 0 */ 145 str w9, [x0, GICD_ISENABLERn] 146 147 /* Initialize Cpu Interface */ 148 mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */ 149 /* Enable Ack Group1 Interrupt & */ 150 /* EnableGrp0 & EnableGrp1 */ 151 str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */ 152 153 mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */ 154 str w9, [x1, GICC_PMR] 155#endif 156 ret 157ENDPROC(gic_init_secure_percpu) 158 159 160/************************************************************************* 161 * For Gicv2: 162 * void gic_kick_secondary_cpus(DistributorBase); 163 * For Gicv3: 164 * void gic_kick_secondary_cpus(void); 165 * 166 *************************************************************************/ 167ENTRY(gic_kick_secondary_cpus) 168#if defined(CONFIG_GICV3) 169 mov x9, #(1 << 40) 170 msr ICC_ASGI1R_EL1, x9 171 isb 172#elif defined(CONFIG_GICV2) 173 mov w9, #0x8000 174 movk w9, #0x100, lsl #16 175 str w9, [x0, GICD_SGIR] 176#endif 177 ret 178ENDPROC(gic_kick_secondary_cpus) 179 180 181/************************************************************************* 182 * For Gicv2: 183 * void gic_wait_for_interrupt(CpuInterfaceBase); 184 * For Gicv3: 185 * void gic_wait_for_interrupt(void); 186 * 187 * Wait for SGI 0 from master. 188 * 189 *************************************************************************/ 190ENTRY(gic_wait_for_interrupt) 191#if defined(CONFIG_GICV3) 192 gic_wait_for_interrupt_m x9 193#elif defined(CONFIG_GICV2) 194 gic_wait_for_interrupt_m x0, w9 195#endif 196 ret 197ENDPROC(gic_wait_for_interrupt) 198