1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* for now: just dummy functions to satisfy the linker */ 9 10 #include <common.h> 11 #include <malloc.h> 12 13 #ifndef CONFIG_SYS_CACHELINE_SIZE 14 #define CONFIG_SYS_CACHELINE_SIZE 32 15 #endif 16 17 /* 18 * Flush range from all levels of d-cache/unified-cache. 19 * Affects the range [start, start + size - 1]. 20 */ 21 __weak void flush_cache(unsigned long start, unsigned long size) 22 { 23 flush_dcache_range(start, start + size); 24 } 25 26 /* 27 * Default implementation: 28 * do a range flush for the entire range 29 */ 30 __weak void flush_dcache_all(void) 31 { 32 flush_cache(0, ~0); 33 } 34 35 /* 36 * Default implementation of enable_caches() 37 * Real implementation should be in platform code 38 */ 39 __weak void enable_caches(void) 40 { 41 puts("WARNING: Caches not enabled\n"); 42 } 43 44 __weak void invalidate_dcache_range(unsigned long start, unsigned long stop) 45 { 46 /* An empty stub, real implementation should be in platform code */ 47 } 48 __weak void flush_dcache_range(unsigned long start, unsigned long stop) 49 { 50 /* An empty stub, real implementation should be in platform code */ 51 } 52 53 int check_cache_range(unsigned long start, unsigned long stop) 54 { 55 int ok = 1; 56 57 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) 58 ok = 0; 59 60 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) 61 ok = 0; 62 63 if (!ok) { 64 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", 65 start, stop); 66 } 67 68 return ok; 69 } 70 71 #ifdef CONFIG_SYS_NONCACHED_MEMORY 72 /* 73 * Reserve one MMU section worth of address space below the malloc() area that 74 * will be mapped uncached. 75 */ 76 static unsigned long noncached_start; 77 static unsigned long noncached_end; 78 static unsigned long noncached_next; 79 80 void noncached_init(void) 81 { 82 phys_addr_t start, end; 83 size_t size; 84 85 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; 86 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); 87 start = end - size; 88 89 debug("mapping memory %pa-%pa non-cached\n", &start, &end); 90 91 noncached_start = start; 92 noncached_end = end; 93 noncached_next = start; 94 95 #ifndef CONFIG_SYS_DCACHE_OFF 96 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); 97 #endif 98 } 99 100 phys_addr_t noncached_alloc(size_t size, size_t align) 101 { 102 phys_addr_t next = ALIGN(noncached_next, align); 103 104 if (next >= noncached_end || (noncached_end - next) < size) 105 return 0; 106 107 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next); 108 noncached_next = next + size; 109 110 return next; 111 } 112 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 113 114 #if defined(CONFIG_SYS_THUMB_BUILD) 115 void invalidate_l2_cache(void) 116 { 117 unsigned int val = 0; 118 119 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 120 : : "r" (val) : "cc"); 121 isb(); 122 } 123 #endif 124