1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/system.h> 26 27 #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) 28 29 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 30 #define CACHE_SETUP 0x1a 31 #else 32 #define CACHE_SETUP 0x1e 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static void cp_delay (void) 38 { 39 volatile int i; 40 41 /* copro seems to need some delay between reading and writing */ 42 for (i = 0; i < 100; i++) 43 nop(); 44 asm volatile("" : : : "memory"); 45 } 46 47 static inline void dram_bank_mmu_setup(int bank) 48 { 49 u32 *page_table = (u32 *)gd->tlb_addr; 50 bd_t *bd = gd->bd; 51 int i; 52 53 debug("%s: bank: %d\n", __func__, bank); 54 for (i = bd->bi_dram[bank].start >> 20; 55 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; 56 i++) { 57 page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP; 58 } 59 } 60 61 /* to activate the MMU we need to set up virtual memory: use 1M areas */ 62 static inline void mmu_setup(void) 63 { 64 u32 *page_table = (u32 *)gd->tlb_addr; 65 int i; 66 u32 reg; 67 68 /* Set up an identity-mapping for all 4GB, rw for everyone */ 69 for (i = 0; i < 4096; i++) 70 page_table[i] = i << 20 | (3 << 10) | 0x12; 71 72 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 73 dram_bank_mmu_setup(i); 74 } 75 76 /* Copy the page table address to cp15 */ 77 asm volatile("mcr p15, 0, %0, c2, c0, 0" 78 : : "r" (page_table) : "memory"); 79 /* Set the access control to all-supervisor */ 80 asm volatile("mcr p15, 0, %0, c3, c0, 0" 81 : : "r" (~0)); 82 /* and enable the mmu */ 83 reg = get_cr(); /* get control reg. */ 84 cp_delay(); 85 set_cr(reg | CR_M); 86 } 87 88 /* cache_bit must be either CR_I or CR_C */ 89 static void cache_enable(uint32_t cache_bit) 90 { 91 uint32_t reg; 92 93 /* The data cache is not active unless the mmu is enabled too */ 94 if (cache_bit == CR_C) 95 mmu_setup(); 96 reg = get_cr(); /* get control reg. */ 97 cp_delay(); 98 set_cr(reg | cache_bit); 99 } 100 101 /* cache_bit must be either CR_I or CR_C */ 102 static void cache_disable(uint32_t cache_bit) 103 { 104 uint32_t reg; 105 106 if (cache_bit == CR_C) { 107 /* if cache isn;t enabled no need to disable */ 108 reg = get_cr(); 109 if ((reg & CR_C) != CR_C) 110 return; 111 /* if disabling data cache, disable mmu too */ 112 cache_bit |= CR_M; 113 flush_cache(0, ~0); 114 } 115 reg = get_cr(); 116 cp_delay(); 117 set_cr(reg & ~cache_bit); 118 } 119 #endif 120 121 #ifdef CONFIG_SYS_NO_ICACHE 122 void icache_enable (void) 123 { 124 return; 125 } 126 127 void icache_disable (void) 128 { 129 return; 130 } 131 132 int icache_status (void) 133 { 134 return 0; /* always off */ 135 } 136 #else 137 void icache_enable(void) 138 { 139 cache_enable(CR_I); 140 } 141 142 void icache_disable(void) 143 { 144 cache_disable(CR_I); 145 } 146 147 int icache_status(void) 148 { 149 return (get_cr() & CR_I) != 0; 150 } 151 #endif 152 153 #ifdef CONFIG_SYS_NO_DCACHE 154 void dcache_enable (void) 155 { 156 return; 157 } 158 159 void dcache_disable (void) 160 { 161 return; 162 } 163 164 int dcache_status (void) 165 { 166 return 0; /* always off */ 167 } 168 #else 169 void dcache_enable(void) 170 { 171 cache_enable(CR_C); 172 } 173 174 void dcache_disable(void) 175 { 176 cache_disable(CR_C); 177 } 178 179 int dcache_status(void) 180 { 181 return (get_cr() & CR_C) != 0; 182 } 183 #endif 184