1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/system.h> 10 #include <asm/cache.h> 11 #include <linux/compiler.h> 12 13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 __weak void arm_init_before_mmu(void) 18 { 19 } 20 21 __weak void arm_init_domains(void) 22 { 23 } 24 25 static void cp_delay (void) 26 { 27 volatile int i; 28 29 /* copro seems to need some delay between reading and writing */ 30 for (i = 0; i < 100; i++) 31 nop(); 32 asm volatile("" : : : "memory"); 33 } 34 35 void set_section_dcache(int section, enum dcache_option option) 36 { 37 #ifdef CONFIG_ARMV7_LPAE 38 u64 *page_table = (u64 *)gd->arch.tlb_addr; 39 /* Need to set the access flag to not fault */ 40 u64 value = TTB_SECT_AP | TTB_SECT_AF; 41 #else 42 u32 *page_table = (u32 *)gd->arch.tlb_addr; 43 u32 value = TTB_SECT_AP; 44 #endif 45 46 /* Add the page offset */ 47 value |= ((u32)section << MMU_SECTION_SHIFT); 48 49 /* Add caching bits */ 50 value |= option; 51 52 /* Set PTE */ 53 page_table[section] = value; 54 } 55 56 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) 57 { 58 debug("%s: Warning: not implemented\n", __func__); 59 } 60 61 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 62 enum dcache_option option) 63 { 64 #ifdef CONFIG_ARMV7_LPAE 65 u64 *page_table = (u64 *)gd->arch.tlb_addr; 66 #else 67 u32 *page_table = (u32 *)gd->arch.tlb_addr; 68 #endif 69 unsigned long startpt, stoppt; 70 unsigned long upto, end; 71 72 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; 73 start = start >> MMU_SECTION_SHIFT; 74 debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size, 75 option); 76 for (upto = start; upto < end; upto++) 77 set_section_dcache(upto, option); 78 79 /* 80 * Make sure range is cache line aligned 81 * Only CPU maintains page tables, hence it is safe to always 82 * flush complete cache lines... 83 */ 84 85 startpt = (unsigned long)&page_table[start]; 86 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); 87 stoppt = (unsigned long)&page_table[end]; 88 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); 89 mmu_page_table_flush(startpt, stoppt); 90 } 91 92 __weak void dram_bank_mmu_setup(int bank) 93 { 94 bd_t *bd = gd->bd; 95 int i; 96 97 debug("%s: bank: %d\n", __func__, bank); 98 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; 99 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + 100 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); 101 i++) { 102 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 103 set_section_dcache(i, DCACHE_WRITETHROUGH); 104 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) 105 set_section_dcache(i, DCACHE_WRITEALLOC); 106 #else 107 set_section_dcache(i, DCACHE_WRITEBACK); 108 #endif 109 } 110 } 111 112 /* to activate the MMU we need to set up virtual memory: use 1M areas */ 113 static inline void mmu_setup(void) 114 { 115 int i; 116 u32 reg; 117 118 arm_init_before_mmu(); 119 /* Set up an identity-mapping for all 4GB, rw for everyone */ 120 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++) 121 set_section_dcache(i, DCACHE_OFF); 122 123 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 124 dram_bank_mmu_setup(i); 125 } 126 127 #ifdef CONFIG_ARMV7_LPAE 128 /* Set up 4 PTE entries pointing to our 4 1GB page tables */ 129 for (i = 0; i < 4; i++) { 130 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4)); 131 u64 tpt = gd->arch.tlb_addr + (4096 * i); 132 page_table[i] = tpt | TTB_PAGETABLE; 133 } 134 135 reg = TTBCR_EAE; 136 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 137 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT; 138 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) 139 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA; 140 #else 141 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; 142 #endif 143 144 if (is_hyp()) { 145 /* Set HCTR to enable LPAE */ 146 asm volatile("mcr p15, 4, %0, c2, c0, 2" 147 : : "r" (reg) : "memory"); 148 /* Set HTTBR0 */ 149 asm volatile("mcrr p15, 4, %0, %1, c2" 150 : 151 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) 152 : "memory"); 153 /* Set HMAIR */ 154 asm volatile("mcr p15, 4, %0, c10, c2, 0" 155 : : "r" (MEMORY_ATTRIBUTES) : "memory"); 156 } else { 157 /* Set TTBCR to enable LPAE */ 158 asm volatile("mcr p15, 0, %0, c2, c0, 2" 159 : : "r" (reg) : "memory"); 160 /* Set 64-bit TTBR0 */ 161 asm volatile("mcrr p15, 0, %0, %1, c2" 162 : 163 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) 164 : "memory"); 165 /* Set MAIR */ 166 asm volatile("mcr p15, 0, %0, c10, c2, 0" 167 : : "r" (MEMORY_ATTRIBUTES) : "memory"); 168 } 169 #elif defined(CONFIG_CPU_V7) 170 /* Set TTBR0 */ 171 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; 172 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 173 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT; 174 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) 175 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA; 176 #else 177 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB; 178 #endif 179 asm volatile("mcr p15, 0, %0, c2, c0, 0" 180 : : "r" (reg) : "memory"); 181 #else 182 /* Copy the page table address to cp15 */ 183 asm volatile("mcr p15, 0, %0, c2, c0, 0" 184 : : "r" (gd->arch.tlb_addr) : "memory"); 185 #endif 186 /* Set the access control to all-supervisor */ 187 asm volatile("mcr p15, 0, %0, c3, c0, 0" 188 : : "r" (~0)); 189 190 arm_init_domains(); 191 192 /* and enable the mmu */ 193 reg = get_cr(); /* get control reg. */ 194 cp_delay(); 195 set_cr(reg | CR_M); 196 } 197 198 static int mmu_enabled(void) 199 { 200 return get_cr() & CR_M; 201 } 202 203 /* cache_bit must be either CR_I or CR_C */ 204 static void cache_enable(uint32_t cache_bit) 205 { 206 uint32_t reg; 207 208 /* The data cache is not active unless the mmu is enabled too */ 209 if ((cache_bit == CR_C) && !mmu_enabled()) 210 mmu_setup(); 211 reg = get_cr(); /* get control reg. */ 212 cp_delay(); 213 set_cr(reg | cache_bit); 214 } 215 216 /* cache_bit must be either CR_I or CR_C */ 217 static void cache_disable(uint32_t cache_bit) 218 { 219 uint32_t reg; 220 221 reg = get_cr(); 222 cp_delay(); 223 224 if (cache_bit == CR_C) { 225 /* if cache isn;t enabled no need to disable */ 226 if ((reg & CR_C) != CR_C) 227 return; 228 /* if disabling data cache, disable mmu too */ 229 cache_bit |= CR_M; 230 } 231 reg = get_cr(); 232 cp_delay(); 233 if (cache_bit == (CR_C | CR_M)) 234 flush_dcache_all(); 235 set_cr(reg & ~cache_bit); 236 } 237 #endif 238 239 #ifdef CONFIG_SYS_ICACHE_OFF 240 void icache_enable (void) 241 { 242 return; 243 } 244 245 void icache_disable (void) 246 { 247 return; 248 } 249 250 int icache_status (void) 251 { 252 return 0; /* always off */ 253 } 254 #else 255 void icache_enable(void) 256 { 257 cache_enable(CR_I); 258 } 259 260 void icache_disable(void) 261 { 262 cache_disable(CR_I); 263 } 264 265 int icache_status(void) 266 { 267 return (get_cr() & CR_I) != 0; 268 } 269 #endif 270 271 #ifdef CONFIG_SYS_DCACHE_OFF 272 void dcache_enable (void) 273 { 274 return; 275 } 276 277 void dcache_disable (void) 278 { 279 return; 280 } 281 282 int dcache_status (void) 283 { 284 return 0; /* always off */ 285 } 286 #else 287 void dcache_enable(void) 288 { 289 cache_enable(CR_C); 290 } 291 292 void dcache_disable(void) 293 { 294 cache_disable(CR_C); 295 } 296 297 int dcache_status(void) 298 { 299 return (get_cr() & CR_C) != 0; 300 } 301 #endif 302