1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/system.h> 10 #include <asm/cache.h> 11 #include <linux/compiler.h> 12 13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 __weak void arm_init_before_mmu(void) 18 { 19 } 20 21 __weak void arm_init_domains(void) 22 { 23 } 24 25 static void cp_delay (void) 26 { 27 volatile int i; 28 29 /* copro seems to need some delay between reading and writing */ 30 for (i = 0; i < 100; i++) 31 nop(); 32 asm volatile("" : : : "memory"); 33 } 34 35 void set_section_dcache(int section, enum dcache_option option) 36 { 37 u32 *page_table = (u32 *)gd->arch.tlb_addr; 38 u32 value; 39 40 value = (section << MMU_SECTION_SHIFT) | (3 << 10); 41 value |= option; 42 page_table[section] = value; 43 } 44 45 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) 46 { 47 debug("%s: Warning: not implemented\n", __func__); 48 } 49 50 void mmu_set_region_dcache_behaviour(u32 start, int size, 51 enum dcache_option option) 52 { 53 u32 *page_table = (u32 *)gd->arch.tlb_addr; 54 u32 upto, end; 55 56 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; 57 start = start >> MMU_SECTION_SHIFT; 58 debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size, 59 option); 60 for (upto = start; upto < end; upto++) 61 set_section_dcache(upto, option); 62 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); 63 } 64 65 __weak void dram_bank_mmu_setup(int bank) 66 { 67 bd_t *bd = gd->bd; 68 int i; 69 70 debug("%s: bank: %d\n", __func__, bank); 71 for (i = bd->bi_dram[bank].start >> 20; 72 i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20); 73 i++) { 74 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 75 set_section_dcache(i, DCACHE_WRITETHROUGH); 76 #else 77 set_section_dcache(i, DCACHE_WRITEBACK); 78 #endif 79 } 80 } 81 82 /* to activate the MMU we need to set up virtual memory: use 1M areas */ 83 static inline void mmu_setup(void) 84 { 85 int i; 86 u32 reg; 87 88 arm_init_before_mmu(); 89 /* Set up an identity-mapping for all 4GB, rw for everyone */ 90 for (i = 0; i < 4096; i++) 91 set_section_dcache(i, DCACHE_OFF); 92 93 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 94 dram_bank_mmu_setup(i); 95 } 96 97 /* Copy the page table address to cp15 */ 98 asm volatile("mcr p15, 0, %0, c2, c0, 0" 99 : : "r" (gd->arch.tlb_addr) : "memory"); 100 /* Set the access control to all-supervisor */ 101 asm volatile("mcr p15, 0, %0, c3, c0, 0" 102 : : "r" (~0)); 103 104 arm_init_domains(); 105 106 /* and enable the mmu */ 107 reg = get_cr(); /* get control reg. */ 108 cp_delay(); 109 set_cr(reg | CR_M); 110 } 111 112 static int mmu_enabled(void) 113 { 114 return get_cr() & CR_M; 115 } 116 117 /* cache_bit must be either CR_I or CR_C */ 118 static void cache_enable(uint32_t cache_bit) 119 { 120 uint32_t reg; 121 122 /* The data cache is not active unless the mmu is enabled too */ 123 if ((cache_bit == CR_C) && !mmu_enabled()) 124 mmu_setup(); 125 reg = get_cr(); /* get control reg. */ 126 cp_delay(); 127 set_cr(reg | cache_bit); 128 } 129 130 /* cache_bit must be either CR_I or CR_C */ 131 static void cache_disable(uint32_t cache_bit) 132 { 133 uint32_t reg; 134 135 reg = get_cr(); 136 cp_delay(); 137 138 if (cache_bit == CR_C) { 139 /* if cache isn;t enabled no need to disable */ 140 if ((reg & CR_C) != CR_C) 141 return; 142 /* if disabling data cache, disable mmu too */ 143 cache_bit |= CR_M; 144 } 145 reg = get_cr(); 146 cp_delay(); 147 if (cache_bit == (CR_C | CR_M)) 148 flush_dcache_all(); 149 set_cr(reg & ~cache_bit); 150 } 151 #endif 152 153 #ifdef CONFIG_SYS_ICACHE_OFF 154 void icache_enable (void) 155 { 156 return; 157 } 158 159 void icache_disable (void) 160 { 161 return; 162 } 163 164 int icache_status (void) 165 { 166 return 0; /* always off */ 167 } 168 #else 169 void icache_enable(void) 170 { 171 cache_enable(CR_I); 172 } 173 174 void icache_disable(void) 175 { 176 cache_disable(CR_I); 177 } 178 179 int icache_status(void) 180 { 181 return (get_cr() & CR_I) != 0; 182 } 183 #endif 184 185 #ifdef CONFIG_SYS_DCACHE_OFF 186 void dcache_enable (void) 187 { 188 return; 189 } 190 191 void dcache_disable (void) 192 { 193 return; 194 } 195 196 int dcache_status (void) 197 { 198 return 0; /* always off */ 199 } 200 #else 201 void dcache_enable(void) 202 { 203 cache_enable(CR_C); 204 } 205 206 void dcache_disable(void) 207 { 208 cache_disable(CR_C); 209 } 210 211 int dcache_status(void) 212 { 213 return (get_cr() & CR_C) != 0; 214 } 215 #endif 216