1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/system.h> 26 #include <asm/cache.h> 27 #include <linux/compiler.h> 28 29 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 void __arm_init_before_mmu(void) 34 { 35 } 36 void arm_init_before_mmu(void) 37 __attribute__((weak, alias("__arm_init_before_mmu"))); 38 39 __weak void arm_init_domains(void) 40 { 41 } 42 43 static void cp_delay (void) 44 { 45 volatile int i; 46 47 /* copro seems to need some delay between reading and writing */ 48 for (i = 0; i < 100; i++) 49 nop(); 50 asm volatile("" : : : "memory"); 51 } 52 53 void set_section_dcache(int section, enum dcache_option option) 54 { 55 u32 *page_table = (u32 *)gd->arch.tlb_addr; 56 u32 value; 57 58 value = (section << MMU_SECTION_SHIFT) | (3 << 10); 59 value |= option; 60 page_table[section] = value; 61 } 62 63 void __mmu_page_table_flush(unsigned long start, unsigned long stop) 64 { 65 debug("%s: Warning: not implemented\n", __func__); 66 } 67 68 void mmu_page_table_flush(unsigned long start, unsigned long stop) 69 __attribute__((weak, alias("__mmu_page_table_flush"))); 70 71 void mmu_set_region_dcache_behaviour(u32 start, int size, 72 enum dcache_option option) 73 { 74 u32 *page_table = (u32 *)gd->arch.tlb_addr; 75 u32 upto, end; 76 77 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; 78 start = start >> MMU_SECTION_SHIFT; 79 debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size, 80 option); 81 for (upto = start; upto < end; upto++) 82 set_section_dcache(upto, option); 83 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); 84 } 85 86 __weak void dram_bank_mmu_setup(int bank) 87 { 88 bd_t *bd = gd->bd; 89 int i; 90 91 debug("%s: bank: %d\n", __func__, bank); 92 for (i = bd->bi_dram[bank].start >> 20; 93 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; 94 i++) { 95 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 96 set_section_dcache(i, DCACHE_WRITETHROUGH); 97 #else 98 set_section_dcache(i, DCACHE_WRITEBACK); 99 #endif 100 } 101 } 102 103 /* to activate the MMU we need to set up virtual memory: use 1M areas */ 104 static inline void mmu_setup(void) 105 { 106 int i; 107 u32 reg; 108 109 arm_init_before_mmu(); 110 /* Set up an identity-mapping for all 4GB, rw for everyone */ 111 for (i = 0; i < 4096; i++) 112 set_section_dcache(i, DCACHE_OFF); 113 114 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 115 dram_bank_mmu_setup(i); 116 } 117 118 /* Copy the page table address to cp15 */ 119 asm volatile("mcr p15, 0, %0, c2, c0, 0" 120 : : "r" (gd->arch.tlb_addr) : "memory"); 121 /* Set the access control to all-supervisor */ 122 asm volatile("mcr p15, 0, %0, c3, c0, 0" 123 : : "r" (~0)); 124 125 arm_init_domains(); 126 127 /* and enable the mmu */ 128 reg = get_cr(); /* get control reg. */ 129 cp_delay(); 130 set_cr(reg | CR_M); 131 } 132 133 static int mmu_enabled(void) 134 { 135 return get_cr() & CR_M; 136 } 137 138 /* cache_bit must be either CR_I or CR_C */ 139 static void cache_enable(uint32_t cache_bit) 140 { 141 uint32_t reg; 142 143 /* The data cache is not active unless the mmu is enabled too */ 144 if ((cache_bit == CR_C) && !mmu_enabled()) 145 mmu_setup(); 146 reg = get_cr(); /* get control reg. */ 147 cp_delay(); 148 set_cr(reg | cache_bit); 149 } 150 151 /* cache_bit must be either CR_I or CR_C */ 152 static void cache_disable(uint32_t cache_bit) 153 { 154 uint32_t reg; 155 156 reg = get_cr(); 157 cp_delay(); 158 159 if (cache_bit == CR_C) { 160 /* if cache isn;t enabled no need to disable */ 161 if ((reg & CR_C) != CR_C) 162 return; 163 /* if disabling data cache, disable mmu too */ 164 cache_bit |= CR_M; 165 } 166 reg = get_cr(); 167 cp_delay(); 168 if (cache_bit == (CR_C | CR_M)) 169 flush_dcache_all(); 170 set_cr(reg & ~cache_bit); 171 } 172 #endif 173 174 #ifdef CONFIG_SYS_ICACHE_OFF 175 void icache_enable (void) 176 { 177 return; 178 } 179 180 void icache_disable (void) 181 { 182 return; 183 } 184 185 int icache_status (void) 186 { 187 return 0; /* always off */ 188 } 189 #else 190 void icache_enable(void) 191 { 192 cache_enable(CR_I); 193 } 194 195 void icache_disable(void) 196 { 197 cache_disable(CR_I); 198 } 199 200 int icache_status(void) 201 { 202 return (get_cr() & CR_I) != 0; 203 } 204 #endif 205 206 #ifdef CONFIG_SYS_DCACHE_OFF 207 void dcache_enable (void) 208 { 209 return; 210 } 211 212 void dcache_disable (void) 213 { 214 return; 215 } 216 217 int dcache_status (void) 218 { 219 return 0; /* always off */ 220 } 221 #else 222 void dcache_enable(void) 223 { 224 cache_enable(CR_C); 225 } 226 227 void dcache_disable(void) 228 { 229 cache_disable(CR_C); 230 } 231 232 int dcache_status(void) 233 { 234 return (get_cr() & CR_C) != 0; 235 } 236 #endif 237