1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/system.h> 10 #include <asm/cache.h> 11 #include <linux/compiler.h> 12 13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 void __arm_init_before_mmu(void) 18 { 19 } 20 void arm_init_before_mmu(void) 21 __attribute__((weak, alias("__arm_init_before_mmu"))); 22 23 __weak void arm_init_domains(void) 24 { 25 } 26 27 static void cp_delay (void) 28 { 29 volatile int i; 30 31 /* copro seems to need some delay between reading and writing */ 32 for (i = 0; i < 100; i++) 33 nop(); 34 asm volatile("" : : : "memory"); 35 } 36 37 void set_section_dcache(int section, enum dcache_option option) 38 { 39 u32 *page_table = (u32 *)gd->arch.tlb_addr; 40 u32 value; 41 42 value = (section << MMU_SECTION_SHIFT) | (3 << 10); 43 value |= option; 44 page_table[section] = value; 45 } 46 47 void __mmu_page_table_flush(unsigned long start, unsigned long stop) 48 { 49 debug("%s: Warning: not implemented\n", __func__); 50 } 51 52 void mmu_page_table_flush(unsigned long start, unsigned long stop) 53 __attribute__((weak, alias("__mmu_page_table_flush"))); 54 55 void mmu_set_region_dcache_behaviour(u32 start, int size, 56 enum dcache_option option) 57 { 58 u32 *page_table = (u32 *)gd->arch.tlb_addr; 59 u32 upto, end; 60 61 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; 62 start = start >> MMU_SECTION_SHIFT; 63 debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size, 64 option); 65 for (upto = start; upto < end; upto++) 66 set_section_dcache(upto, option); 67 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); 68 } 69 70 __weak void dram_bank_mmu_setup(int bank) 71 { 72 bd_t *bd = gd->bd; 73 int i; 74 75 debug("%s: bank: %d\n", __func__, bank); 76 for (i = bd->bi_dram[bank].start >> 20; 77 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; 78 i++) { 79 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 80 set_section_dcache(i, DCACHE_WRITETHROUGH); 81 #else 82 set_section_dcache(i, DCACHE_WRITEBACK); 83 #endif 84 } 85 } 86 87 /* to activate the MMU we need to set up virtual memory: use 1M areas */ 88 static inline void mmu_setup(void) 89 { 90 int i; 91 u32 reg; 92 93 arm_init_before_mmu(); 94 /* Set up an identity-mapping for all 4GB, rw for everyone */ 95 for (i = 0; i < 4096; i++) 96 set_section_dcache(i, DCACHE_OFF); 97 98 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 99 dram_bank_mmu_setup(i); 100 } 101 102 /* Copy the page table address to cp15 */ 103 asm volatile("mcr p15, 0, %0, c2, c0, 0" 104 : : "r" (gd->arch.tlb_addr) : "memory"); 105 /* Set the access control to all-supervisor */ 106 asm volatile("mcr p15, 0, %0, c3, c0, 0" 107 : : "r" (~0)); 108 109 arm_init_domains(); 110 111 /* and enable the mmu */ 112 reg = get_cr(); /* get control reg. */ 113 cp_delay(); 114 set_cr(reg | CR_M); 115 } 116 117 static int mmu_enabled(void) 118 { 119 return get_cr() & CR_M; 120 } 121 122 /* cache_bit must be either CR_I or CR_C */ 123 static void cache_enable(uint32_t cache_bit) 124 { 125 uint32_t reg; 126 127 /* The data cache is not active unless the mmu is enabled too */ 128 if ((cache_bit == CR_C) && !mmu_enabled()) 129 mmu_setup(); 130 reg = get_cr(); /* get control reg. */ 131 cp_delay(); 132 set_cr(reg | cache_bit); 133 } 134 135 /* cache_bit must be either CR_I or CR_C */ 136 static void cache_disable(uint32_t cache_bit) 137 { 138 uint32_t reg; 139 140 reg = get_cr(); 141 cp_delay(); 142 143 if (cache_bit == CR_C) { 144 /* if cache isn;t enabled no need to disable */ 145 if ((reg & CR_C) != CR_C) 146 return; 147 /* if disabling data cache, disable mmu too */ 148 cache_bit |= CR_M; 149 } 150 reg = get_cr(); 151 cp_delay(); 152 if (cache_bit == (CR_C | CR_M)) 153 flush_dcache_all(); 154 set_cr(reg & ~cache_bit); 155 } 156 #endif 157 158 #ifdef CONFIG_SYS_ICACHE_OFF 159 void icache_enable (void) 160 { 161 return; 162 } 163 164 void icache_disable (void) 165 { 166 return; 167 } 168 169 int icache_status (void) 170 { 171 return 0; /* always off */ 172 } 173 #else 174 void icache_enable(void) 175 { 176 cache_enable(CR_I); 177 } 178 179 void icache_disable(void) 180 { 181 cache_disable(CR_I); 182 } 183 184 int icache_status(void) 185 { 186 return (get_cr() & CR_I) != 0; 187 } 188 #endif 189 190 #ifdef CONFIG_SYS_DCACHE_OFF 191 void dcache_enable (void) 192 { 193 return; 194 } 195 196 void dcache_disable (void) 197 { 198 return; 199 } 200 201 int dcache_status (void) 202 { 203 return 0; /* always off */ 204 } 205 #else 206 void dcache_enable(void) 207 { 208 cache_enable(CR_C); 209 } 210 211 void dcache_disable(void) 212 { 213 cache_disable(CR_C); 214 } 215 216 int dcache_status(void) 217 { 218 return (get_cr() & CR_C) != 0; 219 } 220 #endif 221