1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/system.h> 26 27 #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) 28 29 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 30 #define CACHE_SETUP 0x1a 31 #else 32 #define CACHE_SETUP 0x1e 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static void cp_delay (void) 38 { 39 volatile int i; 40 41 /* copro seems to need some delay between reading and writing */ 42 for (i = 0; i < 100; i++) 43 nop(); 44 asm volatile("" : : : "memory"); 45 } 46 47 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 48 static inline void dram_bank_mmu_setup(int bank) 49 { 50 u32 *page_table = (u32 *)gd->tlb_addr; 51 bd_t *bd = gd->bd; 52 int i; 53 54 debug("%s: bank: %d\n", __func__, bank); 55 for (i = bd->bi_dram[bank].start >> 20; 56 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; 57 i++) { 58 page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP; 59 } 60 } 61 #endif 62 63 /* to activate the MMU we need to set up virtual memory: use 1M areas */ 64 static inline void mmu_setup(void) 65 { 66 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 67 u32 *page_table = (u32 *)gd->tlb_addr; 68 #else 69 static u32 __attribute__((aligned(16384))) page_table[4096]; 70 bd_t *bd = gd->bd; 71 int j; 72 #endif 73 int i; 74 u32 reg; 75 76 /* Set up an identity-mapping for all 4GB, rw for everyone */ 77 for (i = 0; i < 4096; i++) 78 page_table[i] = i << 20 | (3 << 10) | 0x12; 79 80 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 81 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 82 dram_bank_mmu_setup(i); 83 } 84 #else 85 /* Then, enable cacheable and bufferable for RAM only */ 86 for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) { 87 for (i = bd->bi_dram[j].start >> 20; 88 i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20; 89 i++) { 90 page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP; 91 } 92 } 93 #endif 94 95 /* Copy the page table address to cp15 */ 96 asm volatile("mcr p15, 0, %0, c2, c0, 0" 97 : : "r" (page_table) : "memory"); 98 /* Set the access control to all-supervisor */ 99 asm volatile("mcr p15, 0, %0, c3, c0, 0" 100 : : "r" (~0)); 101 /* and enable the mmu */ 102 reg = get_cr(); /* get control reg. */ 103 cp_delay(); 104 set_cr(reg | CR_M); 105 } 106 107 /* cache_bit must be either CR_I or CR_C */ 108 static void cache_enable(uint32_t cache_bit) 109 { 110 uint32_t reg; 111 112 /* The data cache is not active unless the mmu is enabled too */ 113 if (cache_bit == CR_C) 114 mmu_setup(); 115 reg = get_cr(); /* get control reg. */ 116 cp_delay(); 117 set_cr(reg | cache_bit); 118 } 119 120 /* cache_bit must be either CR_I or CR_C */ 121 static void cache_disable(uint32_t cache_bit) 122 { 123 uint32_t reg; 124 125 if (cache_bit == CR_C) { 126 /* if cache isn;t enabled no need to disable */ 127 reg = get_cr(); 128 if ((reg & CR_C) != CR_C) 129 return; 130 /* if disabling data cache, disable mmu too */ 131 cache_bit |= CR_M; 132 flush_cache(0, ~0); 133 } 134 reg = get_cr(); 135 cp_delay(); 136 set_cr(reg & ~cache_bit); 137 } 138 #endif 139 140 #ifdef CONFIG_SYS_NO_ICACHE 141 void icache_enable (void) 142 { 143 return; 144 } 145 146 void icache_disable (void) 147 { 148 return; 149 } 150 151 int icache_status (void) 152 { 153 return 0; /* always off */ 154 } 155 #else 156 void icache_enable(void) 157 { 158 cache_enable(CR_I); 159 } 160 161 void icache_disable(void) 162 { 163 cache_disable(CR_I); 164 } 165 166 int icache_status(void) 167 { 168 return (get_cr() & CR_I) != 0; 169 } 170 #endif 171 172 #ifdef CONFIG_SYS_NO_DCACHE 173 void dcache_enable (void) 174 { 175 return; 176 } 177 178 void dcache_disable (void) 179 { 180 return; 181 } 182 183 int dcache_status (void) 184 { 185 return 0; /* always off */ 186 } 187 #else 188 void dcache_enable(void) 189 { 190 cache_enable(CR_C); 191 } 192 193 void dcache_disable(void) 194 { 195 cache_disable(CR_C); 196 } 197 198 int dcache_status(void) 199 { 200 return (get_cr() & CR_C) != 0; 201 } 202 #endif 203