1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * emac definitions for keystone2 devices
4  *
5  * (C) Copyright 2012-2014
6  *     Texas Instruments Incorporated, <www.ti.com>
7  */
8 
9 #ifndef _KEYSTONE_NET_H_
10 #define _KEYSTONE_NET_H_
11 
12 #include <asm/io.h>
13 #include <phy.h>
14 
15 /* EMAC */
16 #ifdef CONFIG_KSNET_NETCP_V1_0
17 
18 #define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00090000)
19 #define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x900)
20 #define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x300)
21 #define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x100)
22 #define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
23 
24 /* Register offsets */
25 #define CPGMACSL_REG_CTL		0x04
26 #define CPGMACSL_REG_STATUS		0x08
27 #define CPGMACSL_REG_RESET		0x0c
28 #define CPGMACSL_REG_MAXLEN		0x10
29 
30 #elif defined CONFIG_KSNET_NETCP_V1_5
31 
32 #define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00200000)
33 #define CPGMACSL_REG_RX_PRI_MAP		0x020
34 #define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x22000)
35 #define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x00f00)
36 #define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x00100)
37 #define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
38 
39 /* Register offsets */
40 #define CPGMACSL_REG_CTL		0x330
41 #define CPGMACSL_REG_STATUS		0x334
42 #define CPGMACSL_REG_RESET		0x338
43 #define CPGMACSL_REG_MAXLEN		0x024
44 
45 #endif
46 
47 #define KEYSTONE2_EMAC_GIG_ENABLE
48 
49 #define MAC_ID_BASE_ADDR		CONFIG_KSNET_MAC_ID_BASE
50 
51 /* MDIO module input frequency */
52 #ifdef CONFIG_SOC_K2G
53 #define EMAC_MDIO_BUS_FREQ		(ks_clk_get_rate(sys_clk0_3_clk))
54 #else
55 #define EMAC_MDIO_BUS_FREQ		(ks_clk_get_rate(pass_pll_clk))
56 #endif
57 /* MDIO clock output frequency */
58 #define EMAC_MDIO_CLOCK_FREQ		2500000	/* 2.5 MHz */
59 
60 #define EMAC_MACCONTROL_MIIEN_ENABLE		0x20
61 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	0x1
62 #define EMAC_MACCONTROL_GIGABIT_ENABLE		BIT(7)
63 #define EMAC_MACCONTROL_GIGFORCE		BIT(17)
64 #define EMAC_MACCONTROL_RMIISPEED_100		BIT(15)
65 
66 #define EMAC_MIN_ETHERNET_PKT_SIZE		60
67 
68 struct mac_sl_cfg {
69 	u_int32_t max_rx_len;	/* Maximum receive packet length. */
70 	u_int32_t ctl;		/* Control bitfield */
71 };
72 
73 /**
74  * Definition: Control bitfields used in the ctl field of mac_sl_cfg
75  */
76 #define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES	BIT(24)
77 #define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES	BIT(23)
78 #define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES	BIT(22)
79 #define GMACSL_RX_ENABLE_EXT_CTL		BIT(18)
80 #define GMACSL_RX_ENABLE_GIG_FORCE		BIT(17)
81 #define GMACSL_RX_ENABLE_IFCTL_B		BIT(16)
82 #define GMACSL_RX_ENABLE_IFCTL_A		BIT(15)
83 #define GMACSL_RX_ENABLE_CMD_IDLE		BIT(11)
84 #define GMACSL_TX_ENABLE_SHORT_GAP		BIT(10)
85 #define GMACSL_ENABLE_GIG_MODE			BIT(7)
86 #define GMACSL_TX_ENABLE_PACE			BIT(6)
87 #define GMACSL_ENABLE				BIT(5)
88 #define GMACSL_TX_ENABLE_FLOW_CTL		BIT(4)
89 #define GMACSL_RX_ENABLE_FLOW_CTL		BIT(3)
90 #define GMACSL_ENABLE_LOOPBACK			BIT(1)
91 #define GMACSL_ENABLE_FULL_DUPLEX		BIT(0)
92 
93 /* EMAC SL function return values */
94 #define GMACSL_RET_OK				0
95 #define GMACSL_RET_INVALID_PORT			-1
96 #define GMACSL_RET_WARN_RESET_INCOMPLETE	-2
97 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG		-3
98 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE	-4
99 
100 /* EMAC SL register definitions */
101 #define DEVICE_EMACSL_RESET_POLL_COUNT		100
102 
103 /* Soft reset register values */
104 #define CPGMAC_REG_RESET_VAL_RESET_MASK		BIT(0)
105 #define CPGMAC_REG_RESET_VAL_RESET		BIT(0)
106 #define CPGMAC_REG_MAXLEN_LEN			0x3fff
107 
108 /* CPSW */
109 /* Control bitfields */
110 #define CPSW_CTL_P2_PASS_PRI_TAGGED		BIT(5)
111 #define CPSW_CTL_P1_PASS_PRI_TAGGED		BIT(4)
112 #define CPSW_CTL_P0_PASS_PRI_TAGGED		BIT(3)
113 #define CPSW_CTL_P0_ENABLE			BIT(2)
114 #define CPSW_CTL_VLAN_AWARE			BIT(1)
115 #define CPSW_CTL_FIFO_LOOPBACK			BIT(0)
116 
117 #define DEVICE_CPSW_NUM_PORTS			CONFIG_KSNET_CPSW_NUM_PORTS
118 #define DEVICE_N_GMACSL_PORTS			(DEVICE_CPSW_NUM_PORTS - 1)
119 
120 #ifdef CONFIG_KSNET_NETCP_V1_0
121 
122 #define DEVICE_CPSW_BASE			(GBETH_BASE + 0x800)
123 #define CPSW_REG_CTL				0x004
124 #define CPSW_REG_STAT_PORT_EN			0x00c
125 #define CPSW_REG_MAXLEN				0x040
126 #define CPSW_REG_ALE_CONTROL			0x608
127 #define CPSW_REG_ALE_PORTCTL(x)			(0x640 + (x) * 4)
128 #define CPSW_REG_VAL_STAT_ENABLE_ALL		0xf
129 
130 #elif defined CONFIG_KSNET_NETCP_V1_5
131 
132 #define DEVICE_CPSW_BASE			(GBETH_BASE + 0x20000)
133 #define CPSW_REG_CTL				0x00004
134 #define CPSW_REG_STAT_PORT_EN			0x00014
135 #define CPSW_REG_MAXLEN				0x01024
136 #define CPSW_REG_ALE_CONTROL			0x1e008
137 #define CPSW_REG_ALE_PORTCTL(x)			(0x1e040 + (x) * 4)
138 #define CPSW_REG_VAL_STAT_ENABLE_ALL		0x1ff
139 
140 #endif
141 
142 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE	((u_int32_t)0xc0000000)
143 #define CPSW_REG_VAL_ALE_CTL_BYPASS		((u_int32_t)0x00000010)
144 #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE	0x3
145 
146 #define target_get_switch_ctl()			CPSW_CTL_P0_ENABLE
147 #define SWITCH_MAX_PKT_SIZE			9000
148 
149 /* SGMII */
150 #define SGMII_REG_STATUS_LOCK			BIT(4)
151 #define SGMII_REG_STATUS_LINK			BIT(0)
152 #define SGMII_REG_STATUS_AUTONEG		BIT(2)
153 #define SGMII_REG_CONTROL_AUTONEG		BIT(0)
154 #define SGMII_REG_CONTROL_MASTER		BIT(5)
155 #define SGMII_REG_MR_ADV_ENABLE			BIT(0)
156 #define SGMII_REG_MR_ADV_LINK			BIT(15)
157 #define SGMII_REG_MR_ADV_FULL_DUPLEX		BIT(12)
158 #define SGMII_REG_MR_ADV_GIG_MODE		BIT(11)
159 
160 #define SGMII_LINK_MAC_MAC_AUTONEG		0
161 #define SGMII_LINK_MAC_PHY			1
162 #define SGMII_LINK_MAC_MAC_FORCED		2
163 #define SGMII_LINK_MAC_FIBER			3
164 #define SGMII_LINK_MAC_PHY_FORCED		4
165 
166 #ifdef CONFIG_KSNET_NETCP_V1_0
167 #define SGMII_OFFSET(x)		((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
168 #elif defined CONFIG_KSNET_NETCP_V1_5
169 #define SGMII_OFFSET(x)		((x) * 0x100)
170 #endif
171 
172 #define SGMII_IDVER_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
173 #define SGMII_SRESET_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
174 #define SGMII_CTL_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
175 #define SGMII_STATUS_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
176 #define SGMII_MRADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
177 #define SGMII_LPADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
178 #define SGMII_TXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
179 #define SGMII_RXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
180 #define SGMII_AUXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
181 
182 /* RGMII */
183 #define RGMII_REG_STATUS_LINK		BIT(0)
184 
185 #define RGMII_STATUS_REG		(GBETH_BASE + 0x18)
186 
187 /* PSS */
188 #ifdef CONFIG_KSNET_NETCP_V1_0
189 
190 #define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x604)
191 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
192 #define hw_config_streaming_switch()\
193 	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
194 
195 #elif defined CONFIG_KSNET_NETCP_V1_5
196 
197 #define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x500)
198 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0
199 
200 #define hw_config_streaming_switch()\
201 	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
202 	       DEVICE_PSTREAM_CFG_REG_ADDR);\
203 	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
204 	       DEVICE_PSTREAM_CFG_REG_ADDR+4);\
205 	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
206 	       DEVICE_PSTREAM_CFG_REG_ADDR+8);\
207 	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
208 	       DEVICE_PSTREAM_CFG_REG_ADDR+12);
209 
210 #endif
211 
212 /* EMAC MDIO Registers Structure */
213 struct mdio_regs {
214 	u32 version;
215 	u32 control;
216 	u32 alive;
217 	u32 link;
218 	u32 linkintraw;
219 	u32 linkintmasked;
220 	u32 rsvd0[2];
221 	u32 userintraw;
222 	u32 userintmasked;
223 	u32 userintmaskset;
224 	u32 userintmaskclear;
225 	u32 rsvd1[20];
226 	u32 useraccess0;
227 	u32 userphysel0;
228 	u32 useraccess1;
229 	u32 userphysel1;
230 };
231 
232 #endif  /* _KEYSTONE_NET_H_ */
233