1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * emac definitions for keystone2 devices 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #ifndef _KEYSTONE_NET_H_ 10 #define _KEYSTONE_NET_H_ 11 12 #include <asm/io.h> 13 #include <phy.h> 14 15 /* EMAC */ 16 #ifdef CONFIG_KSNET_NETCP_V1_0 17 18 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) 19 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) 20 #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) 21 #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) 22 #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040) 23 24 /* Register offsets */ 25 #define CPGMACSL_REG_CTL 0x04 26 #define CPGMACSL_REG_STATUS 0x08 27 #define CPGMACSL_REG_RESET 0x0c 28 #define CPGMACSL_REG_MAXLEN 0x10 29 30 #elif defined CONFIG_KSNET_NETCP_V1_5 31 32 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) 33 #define CPGMACSL_REG_RX_PRI_MAP 0x020 34 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) 35 #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) 36 #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100) 37 #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) 38 39 /* Register offsets */ 40 #define CPGMACSL_REG_CTL 0x330 41 #define CPGMACSL_REG_STATUS 0x334 42 #define CPGMACSL_REG_RESET 0x338 43 #define CPGMACSL_REG_MAXLEN 0x024 44 45 #endif 46 47 #define KEYSTONE2_EMAC_GIG_ENABLE 48 49 #define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE 50 51 /* MDIO module input frequency */ 52 #ifdef CONFIG_SOC_K2G 53 #define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk)) 54 #else 55 #define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk)) 56 #endif 57 /* MDIO clock output frequency */ 58 #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ 59 60 /* MII Status Register */ 61 #define MII_STATUS_REG 1 62 #define MII_STATUS_LINK_MASK 0x4 63 64 #define MDIO_CONTROL_IDLE 0x80000000 65 #define MDIO_CONTROL_ENABLE 0x40000000 66 #define MDIO_CONTROL_FAULT_ENABLE 0x40000 67 #define MDIO_CONTROL_FAULT 0x80000 68 #define MDIO_USERACCESS0_GO 0x80000000 69 #define MDIO_USERACCESS0_WRITE_READ 0x0 70 #define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 71 #define MDIO_USERACCESS0_ACK 0x20000000 72 73 #define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 74 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 75 #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) 76 #define EMAC_MACCONTROL_GIGFORCE BIT(17) 77 #define EMAC_MACCONTROL_RMIISPEED_100 BIT(15) 78 79 #define EMAC_MIN_ETHERNET_PKT_SIZE 60 80 81 struct mac_sl_cfg { 82 u_int32_t max_rx_len; /* Maximum receive packet length. */ 83 u_int32_t ctl; /* Control bitfield */ 84 }; 85 86 /** 87 * Definition: Control bitfields used in the ctl field of mac_sl_cfg 88 */ 89 #define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24) 90 #define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23) 91 #define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22) 92 #define GMACSL_RX_ENABLE_EXT_CTL BIT(18) 93 #define GMACSL_RX_ENABLE_GIG_FORCE BIT(17) 94 #define GMACSL_RX_ENABLE_IFCTL_B BIT(16) 95 #define GMACSL_RX_ENABLE_IFCTL_A BIT(15) 96 #define GMACSL_RX_ENABLE_CMD_IDLE BIT(11) 97 #define GMACSL_TX_ENABLE_SHORT_GAP BIT(10) 98 #define GMACSL_ENABLE_GIG_MODE BIT(7) 99 #define GMACSL_TX_ENABLE_PACE BIT(6) 100 #define GMACSL_ENABLE BIT(5) 101 #define GMACSL_TX_ENABLE_FLOW_CTL BIT(4) 102 #define GMACSL_RX_ENABLE_FLOW_CTL BIT(3) 103 #define GMACSL_ENABLE_LOOPBACK BIT(1) 104 #define GMACSL_ENABLE_FULL_DUPLEX BIT(0) 105 106 /* EMAC SL function return values */ 107 #define GMACSL_RET_OK 0 108 #define GMACSL_RET_INVALID_PORT -1 109 #define GMACSL_RET_WARN_RESET_INCOMPLETE -2 110 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 111 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 112 113 /* EMAC SL register definitions */ 114 #define DEVICE_EMACSL_RESET_POLL_COUNT 100 115 116 /* Soft reset register values */ 117 #define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0) 118 #define CPGMAC_REG_RESET_VAL_RESET BIT(0) 119 #define CPGMAC_REG_MAXLEN_LEN 0x3fff 120 121 /* CPSW */ 122 /* Control bitfields */ 123 #define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5) 124 #define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4) 125 #define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3) 126 #define CPSW_CTL_P0_ENABLE BIT(2) 127 #define CPSW_CTL_VLAN_AWARE BIT(1) 128 #define CPSW_CTL_FIFO_LOOPBACK BIT(0) 129 130 #define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS 131 #define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) 132 133 #ifdef CONFIG_KSNET_NETCP_V1_0 134 135 #define DEVICE_CPSW_BASE (GBETH_BASE + 0x800) 136 #define CPSW_REG_CTL 0x004 137 #define CPSW_REG_STAT_PORT_EN 0x00c 138 #define CPSW_REG_MAXLEN 0x040 139 #define CPSW_REG_ALE_CONTROL 0x608 140 #define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4) 141 #define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf 142 143 #elif defined CONFIG_KSNET_NETCP_V1_5 144 145 #define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000) 146 #define CPSW_REG_CTL 0x00004 147 #define CPSW_REG_STAT_PORT_EN 0x00014 148 #define CPSW_REG_MAXLEN 0x01024 149 #define CPSW_REG_ALE_CONTROL 0x1e008 150 #define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) 151 #define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff 152 153 #endif 154 155 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) 156 #define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) 157 #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 158 159 #define target_get_switch_ctl() CPSW_CTL_P0_ENABLE 160 #define SWITCH_MAX_PKT_SIZE 9000 161 162 /* SGMII */ 163 #define SGMII_REG_STATUS_LOCK BIT(4) 164 #define SGMII_REG_STATUS_LINK BIT(0) 165 #define SGMII_REG_STATUS_AUTONEG BIT(2) 166 #define SGMII_REG_CONTROL_AUTONEG BIT(0) 167 #define SGMII_REG_CONTROL_MASTER BIT(5) 168 #define SGMII_REG_MR_ADV_ENABLE BIT(0) 169 #define SGMII_REG_MR_ADV_LINK BIT(15) 170 #define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) 171 #define SGMII_REG_MR_ADV_GIG_MODE BIT(11) 172 173 #define SGMII_LINK_MAC_MAC_AUTONEG 0 174 #define SGMII_LINK_MAC_PHY 1 175 #define SGMII_LINK_MAC_MAC_FORCED 2 176 #define SGMII_LINK_MAC_FIBER 3 177 #define SGMII_LINK_MAC_PHY_FORCED 4 178 179 #ifdef CONFIG_KSNET_NETCP_V1_0 180 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) 181 #elif defined CONFIG_KSNET_NETCP_V1_5 182 #define SGMII_OFFSET(x) ((x) * 0x100) 183 #endif 184 185 #define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) 186 #define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) 187 #define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) 188 #define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) 189 #define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) 190 #define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) 191 #define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) 192 #define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) 193 #define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) 194 195 /* RGMII */ 196 #define RGMII_REG_STATUS_LINK BIT(0) 197 198 #define RGMII_STATUS_REG (GBETH_BASE + 0x18) 199 200 /* PSS */ 201 #ifdef CONFIG_KSNET_NETCP_V1_0 202 203 #define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) 204 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 205 #define hw_config_streaming_switch()\ 206 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); 207 208 #elif defined CONFIG_KSNET_NETCP_V1_5 209 210 #define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) 211 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 212 213 #define hw_config_streaming_switch()\ 214 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 215 DEVICE_PSTREAM_CFG_REG_ADDR);\ 216 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 217 DEVICE_PSTREAM_CFG_REG_ADDR+4);\ 218 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 219 DEVICE_PSTREAM_CFG_REG_ADDR+8);\ 220 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 221 DEVICE_PSTREAM_CFG_REG_ADDR+12); 222 223 #endif 224 225 /* EMAC MDIO Registers Structure */ 226 struct mdio_regs { 227 u32 version; 228 u32 control; 229 u32 alive; 230 u32 link; 231 u32 linkintraw; 232 u32 linkintmasked; 233 u32 rsvd0[2]; 234 u32 userintraw; 235 u32 userintmasked; 236 u32 userintmaskset; 237 u32 userintmaskclear; 238 u32 rsvd1[20]; 239 u32 useraccess0; 240 u32 userphysel0; 241 u32 useraccess1; 242 u32 userphysel1; 243 }; 244 245 struct eth_priv_t { 246 char int_name[32]; 247 int rx_flow; 248 int phy_addr; 249 int slave_port; 250 int sgmii_link_type; 251 phy_interface_t phy_if; 252 struct phy_device *phy_dev; 253 }; 254 255 int keystone2_emac_initialize(struct eth_priv_t *eth_priv); 256 void sgmii_serdes_setup_156p25mhz(void); 257 void sgmii_serdes_shutdown(void); 258 259 #endif /* _KEYSTONE_NET_H_ */ 260