1 /* 2 * emac definitions for keystone2 devices 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _KEYSTONE_NET_H_ 11 #define _KEYSTONE_NET_H_ 12 13 #include <asm/io.h> 14 #include <phy.h> 15 16 /* EMAC */ 17 #ifdef CONFIG_KSNET_NETCP_V1_0 18 19 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) 20 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) 21 #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) 22 #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) 23 #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040) 24 25 /* Register offsets */ 26 #define CPGMACSL_REG_CTL 0x04 27 #define CPGMACSL_REG_STATUS 0x08 28 #define CPGMACSL_REG_RESET 0x0c 29 #define CPGMACSL_REG_MAXLEN 0x10 30 31 #elif defined CONFIG_KSNET_NETCP_V1_5 32 33 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) 34 #define CPGMACSL_REG_RX_PRI_MAP 0x020 35 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) 36 #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) 37 #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100) 38 #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) 39 40 /* Register offsets */ 41 #define CPGMACSL_REG_CTL 0x330 42 #define CPGMACSL_REG_STATUS 0x334 43 #define CPGMACSL_REG_RESET 0x338 44 #define CPGMACSL_REG_MAXLEN 0x024 45 46 #endif 47 48 #define KEYSTONE2_EMAC_GIG_ENABLE 49 50 #define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE 51 52 /* MDIO module input frequency */ 53 #ifdef CONFIG_SOC_K2G 54 #define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk)) 55 #else 56 #define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk)) 57 #endif 58 /* MDIO clock output frequency */ 59 #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ 60 61 /* MII Status Register */ 62 #define MII_STATUS_REG 1 63 #define MII_STATUS_LINK_MASK 0x4 64 65 #define MDIO_CONTROL_IDLE 0x80000000 66 #define MDIO_CONTROL_ENABLE 0x40000000 67 #define MDIO_CONTROL_FAULT_ENABLE 0x40000 68 #define MDIO_CONTROL_FAULT 0x80000 69 #define MDIO_USERACCESS0_GO 0x80000000 70 #define MDIO_USERACCESS0_WRITE_READ 0x0 71 #define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 72 #define MDIO_USERACCESS0_ACK 0x20000000 73 74 #define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 75 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 76 #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) 77 #define EMAC_MACCONTROL_GIGFORCE BIT(17) 78 #define EMAC_MACCONTROL_RMIISPEED_100 BIT(15) 79 80 #define EMAC_MIN_ETHERNET_PKT_SIZE 60 81 82 struct mac_sl_cfg { 83 u_int32_t max_rx_len; /* Maximum receive packet length. */ 84 u_int32_t ctl; /* Control bitfield */ 85 }; 86 87 /** 88 * Definition: Control bitfields used in the ctl field of mac_sl_cfg 89 */ 90 #define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24) 91 #define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23) 92 #define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22) 93 #define GMACSL_RX_ENABLE_EXT_CTL BIT(18) 94 #define GMACSL_RX_ENABLE_GIG_FORCE BIT(17) 95 #define GMACSL_RX_ENABLE_IFCTL_B BIT(16) 96 #define GMACSL_RX_ENABLE_IFCTL_A BIT(15) 97 #define GMACSL_RX_ENABLE_CMD_IDLE BIT(11) 98 #define GMACSL_TX_ENABLE_SHORT_GAP BIT(10) 99 #define GMACSL_ENABLE_GIG_MODE BIT(7) 100 #define GMACSL_TX_ENABLE_PACE BIT(6) 101 #define GMACSL_ENABLE BIT(5) 102 #define GMACSL_TX_ENABLE_FLOW_CTL BIT(4) 103 #define GMACSL_RX_ENABLE_FLOW_CTL BIT(3) 104 #define GMACSL_ENABLE_LOOPBACK BIT(1) 105 #define GMACSL_ENABLE_FULL_DUPLEX BIT(0) 106 107 /* EMAC SL function return values */ 108 #define GMACSL_RET_OK 0 109 #define GMACSL_RET_INVALID_PORT -1 110 #define GMACSL_RET_WARN_RESET_INCOMPLETE -2 111 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 112 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 113 114 /* EMAC SL register definitions */ 115 #define DEVICE_EMACSL_RESET_POLL_COUNT 100 116 117 /* Soft reset register values */ 118 #define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0) 119 #define CPGMAC_REG_RESET_VAL_RESET BIT(0) 120 #define CPGMAC_REG_MAXLEN_LEN 0x3fff 121 122 /* CPSW */ 123 /* Control bitfields */ 124 #define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5) 125 #define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4) 126 #define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3) 127 #define CPSW_CTL_P0_ENABLE BIT(2) 128 #define CPSW_CTL_VLAN_AWARE BIT(1) 129 #define CPSW_CTL_FIFO_LOOPBACK BIT(0) 130 131 #define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS 132 #define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) 133 134 #ifdef CONFIG_KSNET_NETCP_V1_0 135 136 #define DEVICE_CPSW_BASE (GBETH_BASE + 0x800) 137 #define CPSW_REG_CTL 0x004 138 #define CPSW_REG_STAT_PORT_EN 0x00c 139 #define CPSW_REG_MAXLEN 0x040 140 #define CPSW_REG_ALE_CONTROL 0x608 141 #define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4) 142 #define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf 143 144 #elif defined CONFIG_KSNET_NETCP_V1_5 145 146 #define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000) 147 #define CPSW_REG_CTL 0x00004 148 #define CPSW_REG_STAT_PORT_EN 0x00014 149 #define CPSW_REG_MAXLEN 0x01024 150 #define CPSW_REG_ALE_CONTROL 0x1e008 151 #define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) 152 #define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff 153 154 #endif 155 156 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) 157 #define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) 158 #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 159 160 #define target_get_switch_ctl() CPSW_CTL_P0_ENABLE 161 #define SWITCH_MAX_PKT_SIZE 9000 162 163 /* SGMII */ 164 #define SGMII_REG_STATUS_LOCK BIT(4) 165 #define SGMII_REG_STATUS_LINK BIT(0) 166 #define SGMII_REG_STATUS_AUTONEG BIT(2) 167 #define SGMII_REG_CONTROL_AUTONEG BIT(0) 168 #define SGMII_REG_CONTROL_MASTER BIT(5) 169 #define SGMII_REG_MR_ADV_ENABLE BIT(0) 170 #define SGMII_REG_MR_ADV_LINK BIT(15) 171 #define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) 172 #define SGMII_REG_MR_ADV_GIG_MODE BIT(11) 173 174 #define SGMII_LINK_MAC_MAC_AUTONEG 0 175 #define SGMII_LINK_MAC_PHY 1 176 #define SGMII_LINK_MAC_MAC_FORCED 2 177 #define SGMII_LINK_MAC_FIBER 3 178 #define SGMII_LINK_MAC_PHY_FORCED 4 179 180 #ifdef CONFIG_KSNET_NETCP_V1_0 181 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) 182 #elif defined CONFIG_KSNET_NETCP_V1_5 183 #define SGMII_OFFSET(x) ((x) * 0x100) 184 #endif 185 186 #define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) 187 #define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) 188 #define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) 189 #define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) 190 #define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) 191 #define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) 192 #define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) 193 #define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) 194 #define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) 195 196 /* RGMII */ 197 #define RGMII_REG_STATUS_LINK BIT(0) 198 199 #define RGMII_STATUS_REG (GBETH_BASE + 0x18) 200 201 /* PSS */ 202 #ifdef CONFIG_KSNET_NETCP_V1_0 203 204 #define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) 205 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 206 #define hw_config_streaming_switch()\ 207 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); 208 209 #elif defined CONFIG_KSNET_NETCP_V1_5 210 211 #define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) 212 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 213 214 #define hw_config_streaming_switch()\ 215 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 216 DEVICE_PSTREAM_CFG_REG_ADDR);\ 217 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 218 DEVICE_PSTREAM_CFG_REG_ADDR+4);\ 219 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 220 DEVICE_PSTREAM_CFG_REG_ADDR+8);\ 221 writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ 222 DEVICE_PSTREAM_CFG_REG_ADDR+12); 223 224 #endif 225 226 /* EMAC MDIO Registers Structure */ 227 struct mdio_regs { 228 u32 version; 229 u32 control; 230 u32 alive; 231 u32 link; 232 u32 linkintraw; 233 u32 linkintmasked; 234 u32 rsvd0[2]; 235 u32 userintraw; 236 u32 userintmasked; 237 u32 userintmaskset; 238 u32 userintmaskclear; 239 u32 rsvd1[20]; 240 u32 useraccess0; 241 u32 userphysel0; 242 u32 useraccess1; 243 u32 userphysel1; 244 }; 245 246 struct eth_priv_t { 247 char int_name[32]; 248 int rx_flow; 249 int phy_addr; 250 int slave_port; 251 int sgmii_link_type; 252 phy_interface_t phy_if; 253 struct phy_device *phy_dev; 254 }; 255 256 int keystone2_emac_initialize(struct eth_priv_t *eth_priv); 257 void sgmii_serdes_setup_156p25mhz(void); 258 void sgmii_serdes_shutdown(void); 259 260 #endif /* _KEYSTONE_NET_H_ */ 261