1 /* 2 * Multicore Navigator definitions 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _KEYSTONE_NAV_H_ 11 #define _KEYSTONE_NAV_H_ 12 13 #include <asm/arch/hardware.h> 14 #include <asm/io.h> 15 16 #define QM_OK 0 17 #define QM_ERR -1 18 #define QM_DESC_TYPE_HOST 0 19 #define QM_DESC_PSINFO_IN_DESCR 0 20 #define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \ 21 (QM_DESC_PSINFO_IN_DESCR << 22) 22 23 /* Packet Info */ 24 #define QM_DESC_PINFO_EPIB 1 25 #define QM_DESC_PINFO_RETURN_OWN 1 26 #define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \ 27 (QM_DESC_PINFO_RETURN_OWN << 15) 28 29 struct qm_cfg_reg { 30 u32 revision; 31 u32 __pad1; 32 u32 divert; 33 u32 link_ram_base0; 34 u32 link_ram_size0; 35 u32 link_ram_base1; 36 u32 link_ram_size1; 37 u32 link_ram_base2; 38 u32 starvation[0]; 39 }; 40 41 struct descr_mem_setup_reg { 42 u32 base_addr; 43 u32 start_idx; 44 u32 desc_reg_size; 45 u32 _res0; 46 }; 47 48 struct qm_reg_queue { 49 u32 entry_count; 50 u32 byte_count; 51 u32 packet_size; 52 u32 ptr_size_thresh; 53 }; 54 55 struct qm_config { 56 /* QM module addresses */ 57 u32 stat_cfg; /* status and config */ 58 struct qm_reg_queue *queue; /* management region */ 59 u32 mngr_vbusm; /* management region (VBUSM) */ 60 u32 i_lram; /* internal linking RAM */ 61 struct qm_reg_queue *proxy; 62 u32 status_ram; 63 struct qm_cfg_reg *mngr_cfg; 64 /* Queue manager config region */ 65 u32 intd_cfg; /* QMSS INTD config region */ 66 struct descr_mem_setup_reg *desc_mem; 67 /* descritor memory setup region*/ 68 u32 region_num; 69 u32 pdsp_cmd; /* PDSP1 command interface */ 70 u32 pdsp_ctl; /* PDSP1 control registers */ 71 u32 pdsp_iram; 72 /* QM configuration parameters */ 73 74 u32 qpool_num; /* */ 75 }; 76 77 struct qm_host_desc { 78 u32 desc_info; 79 u32 tag_info; 80 u32 packet_info; 81 u32 buff_len; 82 u32 buff_ptr; 83 u32 next_bdptr; 84 u32 orig_buff_len; 85 u32 orig_buff_ptr; 86 u32 timestamp; 87 u32 swinfo[3]; 88 u32 ps_data[20]; 89 }; 90 91 #define HDESC_NUM 256 92 93 int qm_init(void); 94 void qm_close(void); 95 void qm_push(struct qm_host_desc *hd, u32 qnum); 96 struct qm_host_desc *qm_pop(u32 qnum); 97 98 void qm_buff_push(struct qm_host_desc *hd, u32 qnum, 99 void *buff_ptr, u32 buff_len); 100 101 struct qm_host_desc *qm_pop_from_free_pool(void); 102 void queue_close(u32 qnum); 103 104 /* 105 * DMA API 106 */ 107 #define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \ 108 psloc, sopoff, qmgr, qnum) \ 109 (((einfo & 1) << 30) | \ 110 ((psinfo & 1) << 29) | \ 111 ((rxerr & 1) << 28) | \ 112 ((desc & 3) << 26) | \ 113 ((psloc & 1) << 25) | \ 114 ((sopoff & 0x1ff) << 16) | \ 115 ((qmgr & 3) << 12) | \ 116 ((qnum & 0xfff) << 0)) 117 118 #define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \ 119 (((fd0qm & 3) << 28) | \ 120 ((fd0qnum & 0xfff) << 16) | \ 121 ((fd1qm & 3) << 12) | \ 122 ((fd1qnum & 0xfff) << 0)) 123 124 #define CPDMA_CHAN_A_ENABLE ((u32)1 << 31) 125 #define CPDMA_CHAN_A_TDOWN (1 << 30) 126 #define TDOWN_TIMEOUT_COUNT 100 127 128 struct global_ctl_regs { 129 u32 revision; 130 u32 perf_control; 131 u32 emulation_control; 132 u32 priority_control; 133 u32 qm_base_addr[4]; 134 }; 135 136 struct tx_chan_regs { 137 u32 cfg_a; 138 u32 cfg_b; 139 u32 res[6]; 140 }; 141 142 struct rx_chan_regs { 143 u32 cfg_a; 144 u32 res[7]; 145 }; 146 147 struct rx_flow_regs { 148 u32 control; 149 u32 tags; 150 u32 tag_sel; 151 u32 fdq_sel[2]; 152 u32 thresh[3]; 153 }; 154 155 struct pktdma_cfg { 156 struct global_ctl_regs *global; 157 struct tx_chan_regs *tx_ch; 158 u32 tx_ch_num; 159 struct rx_chan_regs *rx_ch; 160 u32 rx_ch_num; 161 u32 *tx_sched; 162 struct rx_flow_regs *rx_flows; 163 u32 rx_flow_num; 164 165 u32 rx_free_q; 166 u32 rx_rcv_q; 167 u32 tx_snd_q; 168 169 u32 rx_flow; /* flow that is used for RX */ 170 }; 171 172 extern struct pktdma_cfg netcp_pktdma; 173 174 /* 175 * packet dma user allocates memory for rx buffers 176 * and describe it in the following structure 177 */ 178 struct rx_buff_desc { 179 u8 *buff_ptr; 180 u32 num_buffs; 181 u32 buff_len; 182 u32 rx_flow; 183 }; 184 185 int ksnav_close(struct pktdma_cfg *pktdma); 186 int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers); 187 int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2); 188 void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes); 189 void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd); 190 191 #endif /* _KEYSTONE_NAV_H_ */ 192