1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #include <common.h> 5 #include <linux/compiler.h> 6 7 #ifdef CONFIG_ARM64 8 9 /* 10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 11 */ 12 #define CR_M (1 << 0) /* MMU enable */ 13 #define CR_A (1 << 1) /* Alignment abort enable */ 14 #define CR_C (1 << 2) /* Dcache enable */ 15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 16 #define CR_I (1 << 12) /* Icache enable */ 17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 18 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 19 20 #ifndef __ASSEMBLY__ 21 22 u64 get_page_table_size(void); 23 #define PGTABLE_SIZE get_page_table_size() 24 25 /* 2MB granularity */ 26 #define MMU_SECTION_SHIFT 21 27 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) 28 29 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */ 30 enum dcache_option { 31 DCACHE_OFF = 0 << 2, 32 DCACHE_WRITETHROUGH = 3 << 2, 33 DCACHE_WRITEBACK = 4 << 2, 34 DCACHE_WRITEALLOC = 4 << 2, 35 }; 36 37 #define isb() \ 38 ({asm volatile( \ 39 "isb" : : : "memory"); \ 40 }) 41 42 #define wfi() \ 43 ({asm volatile( \ 44 "wfi" : : : "memory"); \ 45 }) 46 47 static inline unsigned int current_el(void) 48 { 49 unsigned int el; 50 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 51 return el >> 2; 52 } 53 54 static inline unsigned int get_sctlr(void) 55 { 56 unsigned int el, val; 57 58 el = current_el(); 59 if (el == 1) 60 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 61 else if (el == 2) 62 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 63 else 64 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 65 66 return val; 67 } 68 69 static inline void set_sctlr(unsigned int val) 70 { 71 unsigned int el; 72 73 el = current_el(); 74 if (el == 1) 75 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 76 else if (el == 2) 77 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 78 else 79 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 80 81 asm volatile("isb"); 82 } 83 84 static inline unsigned long read_mpidr(void) 85 { 86 unsigned long val; 87 88 asm volatile("mrs %0, mpidr_el1" : "=r" (val)); 89 90 return val; 91 } 92 93 #define BSP_COREID 0 94 95 void __asm_flush_dcache_all(void); 96 void __asm_invalidate_dcache_all(void); 97 void __asm_flush_dcache_range(u64 start, u64 end); 98 void __asm_invalidate_tlb_all(void); 99 void __asm_invalidate_icache_all(void); 100 int __asm_flush_l3_cache(void); 101 void __asm_switch_ttbr(u64 new_ttbr); 102 103 void armv8_switch_to_el2(void); 104 void armv8_switch_to_el1(void); 105 void gic_init(void); 106 void gic_send_sgi(unsigned long sgino); 107 void wait_for_wakeup(void); 108 void protect_secure_region(void); 109 void smp_kick_all_cpus(void); 110 111 void flush_l3_cache(void); 112 113 /* 114 *Issue a hypervisor call in accordance with ARM "SMC Calling convention", 115 * DEN0028A 116 * 117 * @args: input and output arguments 118 * 119 */ 120 void hvc_call(struct pt_regs *args); 121 122 /* 123 *Issue a secure monitor call in accordance with ARM "SMC Calling convention", 124 * DEN0028A 125 * 126 * @args: input and output arguments 127 * 128 */ 129 void smc_call(struct pt_regs *args); 130 131 #endif /* __ASSEMBLY__ */ 132 133 #else /* CONFIG_ARM64 */ 134 135 #ifdef __KERNEL__ 136 137 #define CPU_ARCH_UNKNOWN 0 138 #define CPU_ARCH_ARMv3 1 139 #define CPU_ARCH_ARMv4 2 140 #define CPU_ARCH_ARMv4T 3 141 #define CPU_ARCH_ARMv5 4 142 #define CPU_ARCH_ARMv5T 5 143 #define CPU_ARCH_ARMv5TE 6 144 #define CPU_ARCH_ARMv5TEJ 7 145 #define CPU_ARCH_ARMv6 8 146 #define CPU_ARCH_ARMv7 9 147 148 /* 149 * CR1 bits (CP#15 CR1) 150 */ 151 #define CR_M (1 << 0) /* MMU enable */ 152 #define CR_A (1 << 1) /* Alignment abort enable */ 153 #define CR_C (1 << 2) /* Dcache enable */ 154 #define CR_W (1 << 3) /* Write buffer enable */ 155 #define CR_P (1 << 4) /* 32-bit exception handler */ 156 #define CR_D (1 << 5) /* 32-bit data address range */ 157 #define CR_L (1 << 6) /* Implementation defined */ 158 #define CR_B (1 << 7) /* Big endian */ 159 #define CR_S (1 << 8) /* System MMU protection */ 160 #define CR_R (1 << 9) /* ROM MMU protection */ 161 #define CR_F (1 << 10) /* Implementation defined */ 162 #define CR_Z (1 << 11) /* Implementation defined */ 163 #define CR_I (1 << 12) /* Icache enable */ 164 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 165 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 166 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 167 #define CR_DT (1 << 16) 168 #define CR_IT (1 << 18) 169 #define CR_ST (1 << 19) 170 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 171 #define CR_U (1 << 22) /* Unaligned access operation */ 172 #define CR_XP (1 << 23) /* Extended page tables */ 173 #define CR_VE (1 << 24) /* Vectored interrupts */ 174 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 175 #define CR_TRE (1 << 28) /* TEX remap enable */ 176 #define CR_AFE (1 << 29) /* Access flag enable */ 177 #define CR_TE (1 << 30) /* Thumb exception enable */ 178 179 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE) 180 #define PGTABLE_SIZE (4096 * 5) 181 #elif !defined(PGTABLE_SIZE) 182 #define PGTABLE_SIZE (4096 * 4) 183 #endif 184 185 /* 186 * This is used to ensure the compiler did actually allocate the register we 187 * asked it for some inline assembly sequences. Apparently we can't trust 188 * the compiler from one version to another so a bit of paranoia won't hurt. 189 * This string is meant to be concatenated with the inline asm string and 190 * will cause compilation to stop on mismatch. 191 * (for details, see gcc PR 15089) 192 */ 193 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 194 195 #ifndef __ASSEMBLY__ 196 197 /** 198 * save_boot_params() - Save boot parameters before starting reset sequence 199 * 200 * If you provide this function it will be called immediately U-Boot starts, 201 * both for SPL and U-Boot proper. 202 * 203 * All registers are unchanged from U-Boot entry. No registers need be 204 * preserved. 205 * 206 * This is not a normal C function. There is no stack. Return by branching to 207 * save_boot_params_ret. 208 * 209 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 210 */ 211 212 /** 213 * save_boot_params_ret() - Return from save_boot_params() 214 * 215 * If you provide save_boot_params(), then you should jump back to this 216 * function when done. Try to preserve all registers. 217 * 218 * If your implementation of save_boot_params() is in C then it is acceptable 219 * to simply call save_boot_params_ret() at the end of your function. Since 220 * there is no link register set up, you cannot just exit the function. U-Boot 221 * will return to the (initialised) value of lr, and likely crash/hang. 222 * 223 * If your implementation of save_boot_params() is in assembler then you 224 * should use 'b' or 'bx' to return to save_boot_params_ret. 225 */ 226 void save_boot_params_ret(void); 227 228 #define isb() __asm__ __volatile__ ("" : : : "memory") 229 230 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 231 232 #ifdef __ARM_ARCH_7A__ 233 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 234 #else 235 #define wfi() 236 #endif 237 238 static inline unsigned long get_cpsr(void) 239 { 240 unsigned long cpsr; 241 242 asm volatile("mrs %0, cpsr" : "=r"(cpsr): ); 243 return cpsr; 244 } 245 246 static inline int is_hyp(void) 247 { 248 #ifdef CONFIG_ARMV7_LPAE 249 /* HYP mode requires LPAE ... */ 250 return ((get_cpsr() & 0x1f) == 0x1a); 251 #else 252 /* ... so without LPAE support we can optimize all hyp code away */ 253 return 0; 254 #endif 255 } 256 257 static inline unsigned int get_cr(void) 258 { 259 unsigned int val; 260 261 if (is_hyp()) 262 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) 263 : 264 : "cc"); 265 else 266 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) 267 : 268 : "cc"); 269 return val; 270 } 271 272 static inline void set_cr(unsigned int val) 273 { 274 if (is_hyp()) 275 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : 276 : "r" (val) 277 : "cc"); 278 else 279 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : 280 : "r" (val) 281 : "cc"); 282 isb(); 283 } 284 285 static inline unsigned int get_dacr(void) 286 { 287 unsigned int val; 288 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 289 return val; 290 } 291 292 static inline void set_dacr(unsigned int val) 293 { 294 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 295 : : "r" (val) : "cc"); 296 isb(); 297 } 298 299 #ifdef CONFIG_ARMV7_LPAE 300 /* Long-Descriptor Translation Table Level 1/2 Bits */ 301 #define TTB_SECT_XN_MASK (1ULL << 54) 302 #define TTB_SECT_NG_MASK (1 << 11) 303 #define TTB_SECT_AF (1 << 10) 304 #define TTB_SECT_SH_MASK (3 << 8) 305 #define TTB_SECT_NS_MASK (1 << 5) 306 #define TTB_SECT_AP (1 << 6) 307 /* Note: TTB AP bits are set elsewhere */ 308 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */ 309 #define TTB_SECT (1 << 0) 310 #define TTB_PAGETABLE (3 << 0) 311 312 /* TTBCR flags */ 313 #define TTBCR_EAE (1 << 31) 314 #define TTBCR_T0SZ(x) ((x) << 0) 315 #define TTBCR_T1SZ(x) ((x) << 16) 316 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) 317 #define TTBCR_IRGN0_NC (0 << 8) 318 #define TTBCR_IRGN0_WBWA (1 << 8) 319 #define TTBCR_IRGN0_WT (2 << 8) 320 #define TTBCR_IRGN0_WBNWA (3 << 8) 321 #define TTBCR_IRGN0_MASK (3 << 8) 322 #define TTBCR_ORGN0_NC (0 << 10) 323 #define TTBCR_ORGN0_WBWA (1 << 10) 324 #define TTBCR_ORGN0_WT (2 << 10) 325 #define TTBCR_ORGN0_WBNWA (3 << 10) 326 #define TTBCR_ORGN0_MASK (3 << 10) 327 #define TTBCR_SHARED_NON (0 << 12) 328 #define TTBCR_SHARED_OUTER (2 << 12) 329 #define TTBCR_SHARED_INNER (3 << 12) 330 #define TTBCR_EPD0 (0 << 7) 331 332 /* 333 * Memory types 334 */ 335 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \ 336 (0xcc << (2 * 8)) | (0xff << (3 * 8))) 337 338 /* options available for data cache on each page */ 339 enum dcache_option { 340 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0), 341 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), 342 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), 343 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), 344 }; 345 #elif defined(CONFIG_CPU_V7) 346 /* Short-Descriptor Translation Table Level 1 Bits */ 347 #define TTB_SECT_NS_MASK (1 << 19) 348 #define TTB_SECT_NG_MASK (1 << 17) 349 #define TTB_SECT_S_MASK (1 << 16) 350 /* Note: TTB AP bits are set elsewhere */ 351 #define TTB_SECT_AP (3 << 10) 352 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 353 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 354 #define TTB_SECT_XN_MASK (1 << 4) 355 #define TTB_SECT_C_MASK (1 << 3) 356 #define TTB_SECT_B_MASK (1 << 2) 357 #define TTB_SECT (2 << 0) 358 359 /* options available for data cache on each page */ 360 enum dcache_option { 361 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, 362 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 363 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 364 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 365 }; 366 #else 367 #define TTB_SECT_AP (3 << 10) 368 /* options available for data cache on each page */ 369 enum dcache_option { 370 DCACHE_OFF = 0x12, 371 DCACHE_WRITETHROUGH = 0x1a, 372 DCACHE_WRITEBACK = 0x1e, 373 DCACHE_WRITEALLOC = 0x16, 374 }; 375 #endif 376 377 /* Size of an MMU section */ 378 enum { 379 #ifdef CONFIG_ARMV7_LPAE 380 MMU_SECTION_SHIFT = 21, /* 2MB */ 381 #else 382 MMU_SECTION_SHIFT = 20, /* 1MB */ 383 #endif 384 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 385 }; 386 387 #ifdef CONFIG_CPU_V7 388 /* TTBR0 bits */ 389 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 390 #define TTBR0_RGN_NC (0 << 3) 391 #define TTBR0_RGN_WBWA (1 << 3) 392 #define TTBR0_RGN_WT (2 << 3) 393 #define TTBR0_RGN_WB (3 << 3) 394 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 395 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 396 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 397 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 398 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 399 #endif 400 401 /** 402 * Register an update to the page tables, and flush the TLB 403 * 404 * \param start start address of update in page table 405 * \param stop stop address of update in page table 406 */ 407 void mmu_page_table_flush(unsigned long start, unsigned long stop); 408 409 #endif /* __ASSEMBLY__ */ 410 411 #define arch_align_stack(x) (x) 412 413 #endif /* __KERNEL__ */ 414 415 #endif /* CONFIG_ARM64 */ 416 417 #ifndef __ASSEMBLY__ 418 /** 419 * Change the cache settings for a region. 420 * 421 * \param start start address of memory region to change 422 * \param size size of memory region to change 423 * \param option dcache option to select 424 */ 425 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 426 enum dcache_option option); 427 428 #ifdef CONFIG_SYS_NONCACHED_MEMORY 429 void noncached_init(void); 430 phys_addr_t noncached_alloc(size_t size, size_t align); 431 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 432 433 #endif /* __ASSEMBLY__ */ 434 435 #endif 436