1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #include <common.h> 5 #include <linux/compiler.h> 6 7 #ifdef CONFIG_ARM64 8 9 /* 10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 11 */ 12 #define CR_M (1 << 0) /* MMU enable */ 13 #define CR_A (1 << 1) /* Alignment abort enable */ 14 #define CR_C (1 << 2) /* Dcache enable */ 15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 16 #define CR_I (1 << 12) /* Icache enable */ 17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 18 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 19 20 /* 2MB granularity */ 21 #define MMU_SECTION_SHIFT 21 22 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) 23 24 #ifndef __ASSEMBLY__ 25 26 #ifndef CONFIG_SYS_FULL_VA 27 #define PGTABLE_SIZE (0x10000) 28 #else 29 u64 get_page_table_size(void); 30 #define PGTABLE_SIZE get_page_table_size() 31 #endif 32 33 enum dcache_option { 34 DCACHE_OFF = 0x3, 35 }; 36 37 #define isb() \ 38 ({asm volatile( \ 39 "isb" : : : "memory"); \ 40 }) 41 42 #define wfi() \ 43 ({asm volatile( \ 44 "wfi" : : : "memory"); \ 45 }) 46 47 static inline unsigned int current_el(void) 48 { 49 unsigned int el; 50 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 51 return el >> 2; 52 } 53 54 static inline unsigned int get_sctlr(void) 55 { 56 unsigned int el, val; 57 58 el = current_el(); 59 if (el == 1) 60 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 61 else if (el == 2) 62 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 63 else 64 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 65 66 return val; 67 } 68 69 static inline void set_sctlr(unsigned int val) 70 { 71 unsigned int el; 72 73 el = current_el(); 74 if (el == 1) 75 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 76 else if (el == 2) 77 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 78 else 79 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 80 81 asm volatile("isb"); 82 } 83 84 static inline unsigned long read_mpidr(void) 85 { 86 unsigned long val; 87 88 asm volatile("mrs %0, mpidr_el1" : "=r" (val)); 89 90 return val; 91 } 92 93 #define BSP_COREID 0 94 95 void __asm_flush_dcache_all(void); 96 void __asm_invalidate_dcache_all(void); 97 void __asm_flush_dcache_range(u64 start, u64 end); 98 void __asm_invalidate_tlb_all(void); 99 void __asm_invalidate_icache_all(void); 100 int __asm_flush_l3_cache(void); 101 void __asm_switch_ttbr(u64 new_ttbr); 102 103 void armv8_switch_to_el2(void); 104 void armv8_switch_to_el1(void); 105 void gic_init(void); 106 void gic_send_sgi(unsigned long sgino); 107 void wait_for_wakeup(void); 108 void protect_secure_region(void); 109 void smp_kick_all_cpus(void); 110 111 void flush_l3_cache(void); 112 113 /* 114 *Issue a hypervisor call in accordance with ARM "SMC Calling convention", 115 * DEN0028A 116 * 117 * @args: input and output arguments 118 * 119 */ 120 void hvc_call(struct pt_regs *args); 121 122 /* 123 *Issue a secure monitor call in accordance with ARM "SMC Calling convention", 124 * DEN0028A 125 * 126 * @args: input and output arguments 127 * 128 */ 129 void smc_call(struct pt_regs *args); 130 131 #endif /* __ASSEMBLY__ */ 132 133 #else /* CONFIG_ARM64 */ 134 135 #ifdef __KERNEL__ 136 137 #define CPU_ARCH_UNKNOWN 0 138 #define CPU_ARCH_ARMv3 1 139 #define CPU_ARCH_ARMv4 2 140 #define CPU_ARCH_ARMv4T 3 141 #define CPU_ARCH_ARMv5 4 142 #define CPU_ARCH_ARMv5T 5 143 #define CPU_ARCH_ARMv5TE 6 144 #define CPU_ARCH_ARMv5TEJ 7 145 #define CPU_ARCH_ARMv6 8 146 #define CPU_ARCH_ARMv7 9 147 148 /* 149 * CR1 bits (CP#15 CR1) 150 */ 151 #define CR_M (1 << 0) /* MMU enable */ 152 #define CR_A (1 << 1) /* Alignment abort enable */ 153 #define CR_C (1 << 2) /* Dcache enable */ 154 #define CR_W (1 << 3) /* Write buffer enable */ 155 #define CR_P (1 << 4) /* 32-bit exception handler */ 156 #define CR_D (1 << 5) /* 32-bit data address range */ 157 #define CR_L (1 << 6) /* Implementation defined */ 158 #define CR_B (1 << 7) /* Big endian */ 159 #define CR_S (1 << 8) /* System MMU protection */ 160 #define CR_R (1 << 9) /* ROM MMU protection */ 161 #define CR_F (1 << 10) /* Implementation defined */ 162 #define CR_Z (1 << 11) /* Implementation defined */ 163 #define CR_I (1 << 12) /* Icache enable */ 164 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 165 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 166 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 167 #define CR_DT (1 << 16) 168 #define CR_IT (1 << 18) 169 #define CR_ST (1 << 19) 170 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 171 #define CR_U (1 << 22) /* Unaligned access operation */ 172 #define CR_XP (1 << 23) /* Extended page tables */ 173 #define CR_VE (1 << 24) /* Vectored interrupts */ 174 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 175 #define CR_TRE (1 << 28) /* TEX remap enable */ 176 #define CR_AFE (1 << 29) /* Access flag enable */ 177 #define CR_TE (1 << 30) /* Thumb exception enable */ 178 179 #ifndef PGTABLE_SIZE 180 #define PGTABLE_SIZE (4096 * 4) 181 #endif 182 183 /* 184 * This is used to ensure the compiler did actually allocate the register we 185 * asked it for some inline assembly sequences. Apparently we can't trust 186 * the compiler from one version to another so a bit of paranoia won't hurt. 187 * This string is meant to be concatenated with the inline asm string and 188 * will cause compilation to stop on mismatch. 189 * (for details, see gcc PR 15089) 190 */ 191 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 192 193 #ifndef __ASSEMBLY__ 194 195 /** 196 * save_boot_params() - Save boot parameters before starting reset sequence 197 * 198 * If you provide this function it will be called immediately U-Boot starts, 199 * both for SPL and U-Boot proper. 200 * 201 * All registers are unchanged from U-Boot entry. No registers need be 202 * preserved. 203 * 204 * This is not a normal C function. There is no stack. Return by branching to 205 * save_boot_params_ret. 206 * 207 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 208 */ 209 210 /** 211 * save_boot_params_ret() - Return from save_boot_params() 212 * 213 * If you provide save_boot_params(), then you should jump back to this 214 * function when done. Try to preserve all registers. 215 * 216 * If your implementation of save_boot_params() is in C then it is acceptable 217 * to simply call save_boot_params_ret() at the end of your function. Since 218 * there is no link register set up, you cannot just exit the function. U-Boot 219 * will return to the (initialised) value of lr, and likely crash/hang. 220 * 221 * If your implementation of save_boot_params() is in assembler then you 222 * should use 'b' or 'bx' to return to save_boot_params_ret. 223 */ 224 void save_boot_params_ret(void); 225 226 #define isb() __asm__ __volatile__ ("" : : : "memory") 227 228 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 229 230 #ifdef __ARM_ARCH_7A__ 231 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 232 #else 233 #define wfi() 234 #endif 235 236 static inline unsigned int get_cr(void) 237 { 238 unsigned int val; 239 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 240 return val; 241 } 242 243 static inline void set_cr(unsigned int val) 244 { 245 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 246 : : "r" (val) : "cc"); 247 isb(); 248 } 249 250 static inline unsigned int get_dacr(void) 251 { 252 unsigned int val; 253 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 254 return val; 255 } 256 257 static inline void set_dacr(unsigned int val) 258 { 259 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 260 : : "r" (val) : "cc"); 261 isb(); 262 } 263 264 #ifdef CONFIG_CPU_V7 265 /* Short-Descriptor Translation Table Level 1 Bits */ 266 #define TTB_SECT_NS_MASK (1 << 19) 267 #define TTB_SECT_NG_MASK (1 << 17) 268 #define TTB_SECT_S_MASK (1 << 16) 269 /* Note: TTB AP bits are set elsewhere */ 270 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 271 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 272 #define TTB_SECT_XN_MASK (1 << 4) 273 #define TTB_SECT_C_MASK (1 << 3) 274 #define TTB_SECT_B_MASK (1 << 2) 275 #define TTB_SECT (2 << 0) 276 277 /* options available for data cache on each page */ 278 enum dcache_option { 279 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, 280 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 281 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 282 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 283 }; 284 #else 285 /* options available for data cache on each page */ 286 enum dcache_option { 287 DCACHE_OFF = 0x12, 288 DCACHE_WRITETHROUGH = 0x1a, 289 DCACHE_WRITEBACK = 0x1e, 290 DCACHE_WRITEALLOC = 0x16, 291 }; 292 #endif 293 294 /* Size of an MMU section */ 295 enum { 296 MMU_SECTION_SHIFT = 20, 297 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 298 }; 299 300 #ifdef CONFIG_CPU_V7 301 /* TTBR0 bits */ 302 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 303 #define TTBR0_RGN_NC (0 << 3) 304 #define TTBR0_RGN_WBWA (1 << 3) 305 #define TTBR0_RGN_WT (2 << 3) 306 #define TTBR0_RGN_WB (3 << 3) 307 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 308 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 309 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 310 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 311 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 312 #endif 313 314 /** 315 * Register an update to the page tables, and flush the TLB 316 * 317 * \param start start address of update in page table 318 * \param stop stop address of update in page table 319 */ 320 void mmu_page_table_flush(unsigned long start, unsigned long stop); 321 322 #endif /* __ASSEMBLY__ */ 323 324 #define arch_align_stack(x) (x) 325 326 #endif /* __KERNEL__ */ 327 328 #endif /* CONFIG_ARM64 */ 329 330 #ifndef __ASSEMBLY__ 331 /** 332 * Change the cache settings for a region. 333 * 334 * \param start start address of memory region to change 335 * \param size size of memory region to change 336 * \param option dcache option to select 337 */ 338 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 339 enum dcache_option option); 340 341 #ifdef CONFIG_SYS_NONCACHED_MEMORY 342 void noncached_init(void); 343 phys_addr_t noncached_alloc(size_t size, size_t align); 344 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 345 346 #endif /* __ASSEMBLY__ */ 347 348 #endif 349