1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #ifdef CONFIG_ARM64 5 6 /* 7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 8 */ 9 #define CR_M (1 << 0) /* MMU enable */ 10 #define CR_A (1 << 1) /* Alignment abort enable */ 11 #define CR_C (1 << 2) /* Dcache enable */ 12 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 13 #define CR_I (1 << 12) /* Icache enable */ 14 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 15 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 16 17 #define PGTABLE_SIZE (0x10000) 18 19 #ifndef __ASSEMBLY__ 20 21 #define isb() \ 22 ({asm volatile( \ 23 "isb" : : : "memory"); \ 24 }) 25 26 #define wfi() \ 27 ({asm volatile( \ 28 "wfi" : : : "memory"); \ 29 }) 30 31 static inline unsigned int current_el(void) 32 { 33 unsigned int el; 34 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 35 return el >> 2; 36 } 37 38 static inline unsigned int get_sctlr(void) 39 { 40 unsigned int el, val; 41 42 el = current_el(); 43 if (el == 1) 44 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 45 else if (el == 2) 46 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 47 else 48 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 49 50 return val; 51 } 52 53 static inline void set_sctlr(unsigned int val) 54 { 55 unsigned int el; 56 57 el = current_el(); 58 if (el == 1) 59 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 60 else if (el == 2) 61 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 62 else 63 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 64 65 asm volatile("isb"); 66 } 67 68 void __asm_flush_dcache_all(void); 69 void __asm_invalidate_dcache_all(void); 70 void __asm_flush_dcache_range(u64 start, u64 end); 71 void __asm_invalidate_tlb_all(void); 72 void __asm_invalidate_icache_all(void); 73 int __asm_flush_l3_cache(void); 74 75 void armv8_switch_to_el2(void); 76 void armv8_switch_to_el1(void); 77 void gic_init(void); 78 void gic_send_sgi(unsigned long sgino); 79 void wait_for_wakeup(void); 80 void protect_secure_region(void); 81 void smp_kick_all_cpus(void); 82 83 void flush_l3_cache(void); 84 85 #endif /* __ASSEMBLY__ */ 86 87 #else /* CONFIG_ARM64 */ 88 89 #ifdef __KERNEL__ 90 91 #define CPU_ARCH_UNKNOWN 0 92 #define CPU_ARCH_ARMv3 1 93 #define CPU_ARCH_ARMv4 2 94 #define CPU_ARCH_ARMv4T 3 95 #define CPU_ARCH_ARMv5 4 96 #define CPU_ARCH_ARMv5T 5 97 #define CPU_ARCH_ARMv5TE 6 98 #define CPU_ARCH_ARMv5TEJ 7 99 #define CPU_ARCH_ARMv6 8 100 #define CPU_ARCH_ARMv7 9 101 102 /* 103 * CR1 bits (CP#15 CR1) 104 */ 105 #define CR_M (1 << 0) /* MMU enable */ 106 #define CR_A (1 << 1) /* Alignment abort enable */ 107 #define CR_C (1 << 2) /* Dcache enable */ 108 #define CR_W (1 << 3) /* Write buffer enable */ 109 #define CR_P (1 << 4) /* 32-bit exception handler */ 110 #define CR_D (1 << 5) /* 32-bit data address range */ 111 #define CR_L (1 << 6) /* Implementation defined */ 112 #define CR_B (1 << 7) /* Big endian */ 113 #define CR_S (1 << 8) /* System MMU protection */ 114 #define CR_R (1 << 9) /* ROM MMU protection */ 115 #define CR_F (1 << 10) /* Implementation defined */ 116 #define CR_Z (1 << 11) /* Implementation defined */ 117 #define CR_I (1 << 12) /* Icache enable */ 118 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 119 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 120 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 121 #define CR_DT (1 << 16) 122 #define CR_IT (1 << 18) 123 #define CR_ST (1 << 19) 124 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 125 #define CR_U (1 << 22) /* Unaligned access operation */ 126 #define CR_XP (1 << 23) /* Extended page tables */ 127 #define CR_VE (1 << 24) /* Vectored interrupts */ 128 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 129 #define CR_TRE (1 << 28) /* TEX remap enable */ 130 #define CR_AFE (1 << 29) /* Access flag enable */ 131 #define CR_TE (1 << 30) /* Thumb exception enable */ 132 133 #define PGTABLE_SIZE (4096 * 4) 134 135 /* 136 * This is used to ensure the compiler did actually allocate the register we 137 * asked it for some inline assembly sequences. Apparently we can't trust 138 * the compiler from one version to another so a bit of paranoia won't hurt. 139 * This string is meant to be concatenated with the inline asm string and 140 * will cause compilation to stop on mismatch. 141 * (for details, see gcc PR 15089) 142 */ 143 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 144 145 #ifndef __ASSEMBLY__ 146 147 /** 148 * save_boot_params() - Save boot parameters before starting reset sequence 149 * 150 * If you provide this function it will be called immediately U-Boot starts, 151 * both for SPL and U-Boot proper. 152 * 153 * All registers are unchanged from U-Boot entry. No registers need be 154 * preserved. 155 * 156 * This is not a normal C function. There is no stack. Return by branching to 157 * save_boot_params_ret. 158 * 159 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 160 */ 161 162 /** 163 * save_boot_params_ret() - Return from save_boot_params() 164 * 165 * If you provide save_boot_params(), then you should jump back to this 166 * function when done. Try to preserve all registers. 167 * 168 * If your implementation of save_boot_params() is in C then it is acceptable 169 * to simply call save_boot_params_ret() at the end of your function. Since 170 * there is no link register set up, you cannot just exit the function. U-Boot 171 * will return to the (initialised) value of lr, and likely crash/hang. 172 * 173 * If your implementation of save_boot_params() is in assembler then you 174 * should use 'b' or 'bx' to return to save_boot_params_ret. 175 */ 176 void save_boot_params_ret(void); 177 178 #define isb() __asm__ __volatile__ ("" : : : "memory") 179 180 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 181 182 #ifdef __ARM_ARCH_7A__ 183 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 184 #else 185 #define wfi() 186 #endif 187 188 static inline unsigned int get_cr(void) 189 { 190 unsigned int val; 191 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 192 return val; 193 } 194 195 static inline void set_cr(unsigned int val) 196 { 197 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 198 : : "r" (val) : "cc"); 199 isb(); 200 } 201 202 static inline unsigned int get_dacr(void) 203 { 204 unsigned int val; 205 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 206 return val; 207 } 208 209 static inline void set_dacr(unsigned int val) 210 { 211 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 212 : : "r" (val) : "cc"); 213 isb(); 214 } 215 216 #ifdef CONFIG_ARMV7 217 /* Short-Descriptor Translation Table Level 1 Bits */ 218 #define TTB_SECT_NS_MASK (1 << 19) 219 #define TTB_SECT_NG_MASK (1 << 17) 220 #define TTB_SECT_S_MASK (1 << 16) 221 /* Note: TTB AP bits are set elsewhere */ 222 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 223 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 224 #define TTB_SECT_XN_MASK (1 << 4) 225 #define TTB_SECT_C_MASK (1 << 3) 226 #define TTB_SECT_B_MASK (1 << 2) 227 #define TTB_SECT (2 << 0) 228 229 /* options available for data cache on each page */ 230 enum dcache_option { 231 DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | 232 TTB_SECT_XN_MASK | TTB_SECT, 233 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 234 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 235 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 236 }; 237 #else 238 /* options available for data cache on each page */ 239 enum dcache_option { 240 DCACHE_OFF = 0x12, 241 DCACHE_WRITETHROUGH = 0x1a, 242 DCACHE_WRITEBACK = 0x1e, 243 DCACHE_WRITEALLOC = 0x16, 244 }; 245 #endif 246 247 /* Size of an MMU section */ 248 enum { 249 MMU_SECTION_SHIFT = 20, 250 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 251 }; 252 253 #ifdef CONFIG_ARMV7 254 /* TTBR0 bits */ 255 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 256 #define TTBR0_RGN_NC (0 << 3) 257 #define TTBR0_RGN_WBWA (1 << 3) 258 #define TTBR0_RGN_WT (2 << 3) 259 #define TTBR0_RGN_WB (3 << 3) 260 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 261 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 262 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 263 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 264 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 265 #endif 266 267 /** 268 * Change the cache settings for a region. 269 * 270 * \param start start address of memory region to change 271 * \param size size of memory region to change 272 * \param option dcache option to select 273 */ 274 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 275 enum dcache_option option); 276 277 /** 278 * Register an update to the page tables, and flush the TLB 279 * 280 * \param start start address of update in page table 281 * \param stop stop address of update in page table 282 */ 283 void mmu_page_table_flush(unsigned long start, unsigned long stop); 284 285 #ifdef CONFIG_SYS_NONCACHED_MEMORY 286 void noncached_init(void); 287 phys_addr_t noncached_alloc(size_t size, size_t align); 288 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 289 290 #endif /* __ASSEMBLY__ */ 291 292 #define arch_align_stack(x) (x) 293 294 #endif /* __KERNEL__ */ 295 296 #endif /* CONFIG_ARM64 */ 297 298 #endif 299