1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #include <common.h> 5 #include <linux/compiler.h> 6 #include <asm/barriers.h> 7 8 #ifdef CONFIG_ARM64 9 10 /* 11 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 12 */ 13 #define CR_M (1 << 0) /* MMU enable */ 14 #define CR_A (1 << 1) /* Alignment abort enable */ 15 #define CR_C (1 << 2) /* Dcache enable */ 16 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 17 #define CR_I (1 << 12) /* Icache enable */ 18 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 19 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 20 21 #define ES_TO_AARCH64 1 22 #define ES_TO_AARCH32 0 23 24 /* 25 * SCR_EL3 bits definitions 26 */ 27 #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */ 28 #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */ 29 #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */ 30 #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */ 31 #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */ 32 #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */ 33 34 /* 35 * SPSR_EL3/SPSR_EL2 bits definitions 36 */ 37 #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */ 38 #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */ 39 #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */ 40 #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */ 41 #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */ 42 #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */ 43 #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */ 44 #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */ 45 #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */ 46 #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */ 47 #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */ 48 #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */ 49 #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */ 50 51 /* 52 * CPTR_EL2 bits definitions 53 */ 54 #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */ 55 56 /* 57 * SCTLR_EL2 bits definitions 58 */ 59 #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\ 60 1 << 11 | 3 << 4) /* Reserved, RES1 */ 61 #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */ 62 #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */ 63 #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ 64 #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */ 65 #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */ 66 #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */ 67 #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */ 68 69 /* 70 * CNTHCTL_EL2 bits definitions 71 */ 72 #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ 73 #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ 74 75 /* 76 * HCR_EL2 bits definitions 77 */ 78 #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */ 79 #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ 80 #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ 81 82 /* 83 * CPACR_EL1 bits definitions 84 */ 85 #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */ 86 87 /* 88 * SCTLR_EL1 bits definitions 89 */ 90 #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\ 91 1 << 11) /* Reserved, RES1 */ 92 #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */ 93 #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */ 94 #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */ 95 #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */ 96 #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */ 97 #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */ 98 #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */ 99 #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ 100 #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */ 101 #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */ 102 #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */ 103 #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */ 104 #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */ 105 #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */ 106 #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */ 107 #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */ 108 #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */ 109 110 #ifndef __ASSEMBLY__ 111 112 u64 get_page_table_size(void); 113 #define PGTABLE_SIZE get_page_table_size() 114 115 /* 2MB granularity */ 116 #define MMU_SECTION_SHIFT 21 117 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) 118 119 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */ 120 enum dcache_option { 121 DCACHE_OFF = 0 << 2, 122 DCACHE_WRITETHROUGH = 3 << 2, 123 DCACHE_WRITEBACK = 4 << 2, 124 DCACHE_WRITEALLOC = 4 << 2, 125 }; 126 127 #define wfi() \ 128 ({asm volatile( \ 129 "wfi" : : : "memory"); \ 130 }) 131 132 static inline unsigned int current_el(void) 133 { 134 unsigned int el; 135 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 136 return el >> 2; 137 } 138 139 static inline unsigned int get_sctlr(void) 140 { 141 unsigned int el, val; 142 143 el = current_el(); 144 if (el == 1) 145 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 146 else if (el == 2) 147 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 148 else 149 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 150 151 return val; 152 } 153 154 static inline void set_sctlr(unsigned int val) 155 { 156 unsigned int el; 157 158 el = current_el(); 159 if (el == 1) 160 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 161 else if (el == 2) 162 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 163 else 164 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 165 166 asm volatile("isb"); 167 } 168 169 static inline unsigned long read_mpidr(void) 170 { 171 unsigned long val; 172 173 asm volatile("mrs %0, mpidr_el1" : "=r" (val)); 174 175 return val; 176 } 177 178 #define BSP_COREID 0 179 180 void __asm_flush_dcache_all(void); 181 void __asm_invalidate_dcache_all(void); 182 void __asm_flush_dcache_range(u64 start, u64 end); 183 void __asm_invalidate_tlb_all(void); 184 void __asm_invalidate_icache_all(void); 185 int __asm_invalidate_l3_dcache(void); 186 int __asm_flush_l3_dcache(void); 187 int __asm_invalidate_l3_icache(void); 188 void __asm_switch_ttbr(u64 new_ttbr); 189 190 /* 191 * Switch from EL3 to EL2 for ARMv8 192 * 193 * @args: For loading 64-bit OS, fdt address. 194 * For loading 32-bit OS, zero. 195 * @mach_nr: For loading 64-bit OS, zero. 196 * For loading 32-bit OS, machine nr 197 * @fdt_addr: For loading 64-bit OS, zero. 198 * For loading 32-bit OS, fdt address. 199 * @entry_point: kernel entry point 200 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 201 */ 202 void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, 203 u64 entry_point, u64 es_flag); 204 /* 205 * Switch from EL2 to EL1 for ARMv8 206 * 207 * @args: For loading 64-bit OS, fdt address. 208 * For loading 32-bit OS, zero. 209 * @mach_nr: For loading 64-bit OS, zero. 210 * For loading 32-bit OS, machine nr 211 * @fdt_addr: For loading 64-bit OS, zero. 212 * For loading 32-bit OS, fdt address. 213 * @entry_point: kernel entry point 214 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 215 */ 216 void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr, 217 u64 entry_point, u64 es_flag); 218 void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr, 219 u64 entry_point); 220 void gic_init(void); 221 void gic_send_sgi(unsigned long sgino); 222 void wait_for_wakeup(void); 223 void protect_secure_region(void); 224 void smp_kick_all_cpus(void); 225 226 void flush_l3_cache(void); 227 228 /* 229 *Issue a secure monitor call in accordance with ARM "SMC Calling convention", 230 * DEN0028A 231 * 232 * @args: input and output arguments 233 * 234 */ 235 void smc_call(struct pt_regs *args); 236 237 void __noreturn psci_system_reset(void); 238 void __noreturn psci_system_off(void); 239 240 #endif /* __ASSEMBLY__ */ 241 242 #else /* CONFIG_ARM64 */ 243 244 #ifdef __KERNEL__ 245 246 #define CPU_ARCH_UNKNOWN 0 247 #define CPU_ARCH_ARMv3 1 248 #define CPU_ARCH_ARMv4 2 249 #define CPU_ARCH_ARMv4T 3 250 #define CPU_ARCH_ARMv5 4 251 #define CPU_ARCH_ARMv5T 5 252 #define CPU_ARCH_ARMv5TE 6 253 #define CPU_ARCH_ARMv5TEJ 7 254 #define CPU_ARCH_ARMv6 8 255 #define CPU_ARCH_ARMv7 9 256 257 /* 258 * CR1 bits (CP#15 CR1) 259 */ 260 #define CR_M (1 << 0) /* MMU enable */ 261 #define CR_A (1 << 1) /* Alignment abort enable */ 262 #define CR_C (1 << 2) /* Dcache enable */ 263 #define CR_W (1 << 3) /* Write buffer enable */ 264 #define CR_P (1 << 4) /* 32-bit exception handler */ 265 #define CR_D (1 << 5) /* 32-bit data address range */ 266 #define CR_L (1 << 6) /* Implementation defined */ 267 #define CR_B (1 << 7) /* Big endian */ 268 #define CR_S (1 << 8) /* System MMU protection */ 269 #define CR_R (1 << 9) /* ROM MMU protection */ 270 #define CR_F (1 << 10) /* Implementation defined */ 271 #define CR_Z (1 << 11) /* Implementation defined */ 272 #define CR_I (1 << 12) /* Icache enable */ 273 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 274 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 275 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 276 #define CR_DT (1 << 16) 277 #define CR_IT (1 << 18) 278 #define CR_ST (1 << 19) 279 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 280 #define CR_U (1 << 22) /* Unaligned access operation */ 281 #define CR_XP (1 << 23) /* Extended page tables */ 282 #define CR_VE (1 << 24) /* Vectored interrupts */ 283 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 284 #define CR_TRE (1 << 28) /* TEX remap enable */ 285 #define CR_AFE (1 << 29) /* Access flag enable */ 286 #define CR_TE (1 << 30) /* Thumb exception enable */ 287 288 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE) 289 #define PGTABLE_SIZE (4096 * 5) 290 #elif !defined(PGTABLE_SIZE) 291 #define PGTABLE_SIZE (4096 * 4) 292 #endif 293 294 /* 295 * This is used to ensure the compiler did actually allocate the register we 296 * asked it for some inline assembly sequences. Apparently we can't trust 297 * the compiler from one version to another so a bit of paranoia won't hurt. 298 * This string is meant to be concatenated with the inline asm string and 299 * will cause compilation to stop on mismatch. 300 * (for details, see gcc PR 15089) 301 */ 302 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 303 304 #ifndef __ASSEMBLY__ 305 306 /** 307 * save_boot_params() - Save boot parameters before starting reset sequence 308 * 309 * If you provide this function it will be called immediately U-Boot starts, 310 * both for SPL and U-Boot proper. 311 * 312 * All registers are unchanged from U-Boot entry. No registers need be 313 * preserved. 314 * 315 * This is not a normal C function. There is no stack. Return by branching to 316 * save_boot_params_ret. 317 * 318 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 319 */ 320 321 /** 322 * save_boot_params_ret() - Return from save_boot_params() 323 * 324 * If you provide save_boot_params(), then you should jump back to this 325 * function when done. Try to preserve all registers. 326 * 327 * If your implementation of save_boot_params() is in C then it is acceptable 328 * to simply call save_boot_params_ret() at the end of your function. Since 329 * there is no link register set up, you cannot just exit the function. U-Boot 330 * will return to the (initialised) value of lr, and likely crash/hang. 331 * 332 * If your implementation of save_boot_params() is in assembler then you 333 * should use 'b' or 'bx' to return to save_boot_params_ret. 334 */ 335 void save_boot_params_ret(void); 336 337 #ifdef CONFIG_ARMV7_LPAE 338 void switch_to_hypervisor_ret(void); 339 #endif 340 341 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 342 343 #ifdef __ARM_ARCH_7A__ 344 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 345 #else 346 #define wfi() 347 #endif 348 349 static inline unsigned long get_cpsr(void) 350 { 351 unsigned long cpsr; 352 353 asm volatile("mrs %0, cpsr" : "=r"(cpsr): ); 354 return cpsr; 355 } 356 357 static inline int is_hyp(void) 358 { 359 #ifdef CONFIG_ARMV7_LPAE 360 /* HYP mode requires LPAE ... */ 361 return ((get_cpsr() & 0x1f) == 0x1a); 362 #else 363 /* ... so without LPAE support we can optimize all hyp code away */ 364 return 0; 365 #endif 366 } 367 368 static inline unsigned int get_cr(void) 369 { 370 unsigned int val; 371 372 if (is_hyp()) 373 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) 374 : 375 : "cc"); 376 else 377 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) 378 : 379 : "cc"); 380 return val; 381 } 382 383 static inline void set_cr(unsigned int val) 384 { 385 if (is_hyp()) 386 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : 387 : "r" (val) 388 : "cc"); 389 else 390 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : 391 : "r" (val) 392 : "cc"); 393 isb(); 394 } 395 396 static inline unsigned int get_dacr(void) 397 { 398 unsigned int val; 399 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 400 return val; 401 } 402 403 static inline void set_dacr(unsigned int val) 404 { 405 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 406 : : "r" (val) : "cc"); 407 isb(); 408 } 409 410 #ifdef CONFIG_ARMV7_LPAE 411 /* Long-Descriptor Translation Table Level 1/2 Bits */ 412 #define TTB_SECT_XN_MASK (1ULL << 54) 413 #define TTB_SECT_NG_MASK (1 << 11) 414 #define TTB_SECT_AF (1 << 10) 415 #define TTB_SECT_SH_MASK (3 << 8) 416 #define TTB_SECT_NS_MASK (1 << 5) 417 #define TTB_SECT_AP (1 << 6) 418 /* Note: TTB AP bits are set elsewhere */ 419 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */ 420 #define TTB_SECT (1 << 0) 421 #define TTB_PAGETABLE (3 << 0) 422 423 /* TTBCR flags */ 424 #define TTBCR_EAE (1 << 31) 425 #define TTBCR_T0SZ(x) ((x) << 0) 426 #define TTBCR_T1SZ(x) ((x) << 16) 427 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) 428 #define TTBCR_IRGN0_NC (0 << 8) 429 #define TTBCR_IRGN0_WBWA (1 << 8) 430 #define TTBCR_IRGN0_WT (2 << 8) 431 #define TTBCR_IRGN0_WBNWA (3 << 8) 432 #define TTBCR_IRGN0_MASK (3 << 8) 433 #define TTBCR_ORGN0_NC (0 << 10) 434 #define TTBCR_ORGN0_WBWA (1 << 10) 435 #define TTBCR_ORGN0_WT (2 << 10) 436 #define TTBCR_ORGN0_WBNWA (3 << 10) 437 #define TTBCR_ORGN0_MASK (3 << 10) 438 #define TTBCR_SHARED_NON (0 << 12) 439 #define TTBCR_SHARED_OUTER (2 << 12) 440 #define TTBCR_SHARED_INNER (3 << 12) 441 #define TTBCR_EPD0 (0 << 7) 442 443 /* 444 * Memory types 445 */ 446 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \ 447 (0xcc << (2 * 8)) | (0xff << (3 * 8))) 448 449 /* options available for data cache on each page */ 450 enum dcache_option { 451 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, 452 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), 453 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), 454 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), 455 }; 456 #elif defined(CONFIG_CPU_V7) 457 /* Short-Descriptor Translation Table Level 1 Bits */ 458 #define TTB_SECT_NS_MASK (1 << 19) 459 #define TTB_SECT_NG_MASK (1 << 17) 460 #define TTB_SECT_S_MASK (1 << 16) 461 /* Note: TTB AP bits are set elsewhere */ 462 #define TTB_SECT_AP (3 << 10) 463 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 464 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 465 #define TTB_SECT_XN_MASK (1 << 4) 466 #define TTB_SECT_C_MASK (1 << 3) 467 #define TTB_SECT_B_MASK (1 << 2) 468 #define TTB_SECT (2 << 0) 469 470 /* options available for data cache on each page */ 471 enum dcache_option { 472 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, 473 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 474 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 475 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 476 }; 477 #else 478 #define TTB_SECT_AP (3 << 10) 479 /* options available for data cache on each page */ 480 enum dcache_option { 481 DCACHE_OFF = 0x12, 482 DCACHE_WRITETHROUGH = 0x1a, 483 DCACHE_WRITEBACK = 0x1e, 484 DCACHE_WRITEALLOC = 0x16, 485 }; 486 #endif 487 488 /* Size of an MMU section */ 489 enum { 490 #ifdef CONFIG_ARMV7_LPAE 491 MMU_SECTION_SHIFT = 21, /* 2MB */ 492 #else 493 MMU_SECTION_SHIFT = 20, /* 1MB */ 494 #endif 495 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 496 }; 497 498 #ifdef CONFIG_CPU_V7 499 /* TTBR0 bits */ 500 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 501 #define TTBR0_RGN_NC (0 << 3) 502 #define TTBR0_RGN_WBWA (1 << 3) 503 #define TTBR0_RGN_WT (2 << 3) 504 #define TTBR0_RGN_WB (3 << 3) 505 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 506 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 507 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 508 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 509 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 510 #endif 511 512 /** 513 * Register an update to the page tables, and flush the TLB 514 * 515 * \param start start address of update in page table 516 * \param stop stop address of update in page table 517 */ 518 void mmu_page_table_flush(unsigned long start, unsigned long stop); 519 520 #endif /* __ASSEMBLY__ */ 521 522 #define arch_align_stack(x) (x) 523 524 #endif /* __KERNEL__ */ 525 526 #endif /* CONFIG_ARM64 */ 527 528 #ifndef __ASSEMBLY__ 529 /** 530 * Change the cache settings for a region. 531 * 532 * \param start start address of memory region to change 533 * \param size size of memory region to change 534 * \param option dcache option to select 535 */ 536 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 537 enum dcache_option option); 538 539 #ifdef CONFIG_SYS_NONCACHED_MEMORY 540 void noncached_init(void); 541 phys_addr_t noncached_alloc(size_t size, size_t align); 542 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 543 544 #endif /* __ASSEMBLY__ */ 545 546 #endif 547