1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #ifdef __KERNEL__ 5 6 #define CPU_ARCH_UNKNOWN 0 7 #define CPU_ARCH_ARMv3 1 8 #define CPU_ARCH_ARMv4 2 9 #define CPU_ARCH_ARMv4T 3 10 #define CPU_ARCH_ARMv5 4 11 #define CPU_ARCH_ARMv5T 5 12 #define CPU_ARCH_ARMv5TE 6 13 #define CPU_ARCH_ARMv5TEJ 7 14 #define CPU_ARCH_ARMv6 8 15 #define CPU_ARCH_ARMv7 9 16 17 /* 18 * CR1 bits (CP#15 CR1) 19 */ 20 #define CR_M (1 << 0) /* MMU enable */ 21 #define CR_A (1 << 1) /* Alignment abort enable */ 22 #define CR_C (1 << 2) /* Dcache enable */ 23 #define CR_W (1 << 3) /* Write buffer enable */ 24 #define CR_P (1 << 4) /* 32-bit exception handler */ 25 #define CR_D (1 << 5) /* 32-bit data address range */ 26 #define CR_L (1 << 6) /* Implementation defined */ 27 #define CR_B (1 << 7) /* Big endian */ 28 #define CR_S (1 << 8) /* System MMU protection */ 29 #define CR_R (1 << 9) /* ROM MMU protection */ 30 #define CR_F (1 << 10) /* Implementation defined */ 31 #define CR_Z (1 << 11) /* Implementation defined */ 32 #define CR_I (1 << 12) /* Icache enable */ 33 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 34 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 35 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 36 #define CR_DT (1 << 16) 37 #define CR_IT (1 << 18) 38 #define CR_ST (1 << 19) 39 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 40 #define CR_U (1 << 22) /* Unaligned access operation */ 41 #define CR_XP (1 << 23) /* Extended page tables */ 42 #define CR_VE (1 << 24) /* Vectored interrupts */ 43 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 44 #define CR_TRE (1 << 28) /* TEX remap enable */ 45 #define CR_AFE (1 << 29) /* Access flag enable */ 46 #define CR_TE (1 << 30) /* Thumb exception enable */ 47 48 /* 49 * This is used to ensure the compiler did actually allocate the register we 50 * asked it for some inline assembly sequences. Apparently we can't trust 51 * the compiler from one version to another so a bit of paranoia won't hurt. 52 * This string is meant to be concatenated with the inline asm string and 53 * will cause compilation to stop on mismatch. 54 * (for details, see gcc PR 15089) 55 */ 56 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 57 58 #ifndef __ASSEMBLY__ 59 60 #define isb() __asm__ __volatile__ ("" : : : "memory") 61 62 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 63 64 static inline unsigned int get_cr(void) 65 { 66 unsigned int val; 67 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 68 return val; 69 } 70 71 static inline void set_cr(unsigned int val) 72 { 73 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 74 : : "r" (val) : "cc"); 75 isb(); 76 } 77 78 /* options available for data cache on each page */ 79 enum dcache_option { 80 DCACHE_OFF = 0x12, 81 DCACHE_WRITETHROUGH = 0x1a, 82 DCACHE_WRITEBACK = 0x1e, 83 }; 84 85 /* Size of an MMU section */ 86 enum { 87 MMU_SECTION_SHIFT = 20, 88 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 89 }; 90 91 /** 92 * Change the cache settings for a region. 93 * 94 * \param start start address of memory region to change 95 * \param size size of memory region to change 96 * \param option dcache option to select 97 */ 98 void mmu_set_region_dcache_behaviour(u32 start, int size, 99 enum dcache_option option); 100 101 /** 102 * Register an update to the page tables, and flush the TLB 103 * 104 * \param start start address of update in page table 105 * \param stop stop address of update in page table 106 */ 107 void mmu_page_table_flush(unsigned long start, unsigned long stop); 108 109 #endif /* __ASSEMBLY__ */ 110 111 #define arch_align_stack(x) (x) 112 113 #endif /* __KERNEL__ */ 114 115 #endif 116