1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #include <common.h> 5 #include <linux/compiler.h> 6 7 #ifdef CONFIG_ARM64 8 9 /* 10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 11 */ 12 #define CR_M (1 << 0) /* MMU enable */ 13 #define CR_A (1 << 1) /* Alignment abort enable */ 14 #define CR_C (1 << 2) /* Dcache enable */ 15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 16 #define CR_I (1 << 12) /* Icache enable */ 17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 18 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 19 20 #ifndef CONFIG_SYS_FULL_VA 21 #define PGTABLE_SIZE (0x10000) 22 #else 23 #define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE 24 #endif 25 26 /* 2MB granularity */ 27 #define MMU_SECTION_SHIFT 21 28 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) 29 30 #ifndef __ASSEMBLY__ 31 32 enum dcache_option { 33 DCACHE_OFF = 0x3, 34 }; 35 36 #define isb() \ 37 ({asm volatile( \ 38 "isb" : : : "memory"); \ 39 }) 40 41 #define wfi() \ 42 ({asm volatile( \ 43 "wfi" : : : "memory"); \ 44 }) 45 46 static inline unsigned int current_el(void) 47 { 48 unsigned int el; 49 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 50 return el >> 2; 51 } 52 53 static inline unsigned int get_sctlr(void) 54 { 55 unsigned int el, val; 56 57 el = current_el(); 58 if (el == 1) 59 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 60 else if (el == 2) 61 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 62 else 63 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 64 65 return val; 66 } 67 68 static inline void set_sctlr(unsigned int val) 69 { 70 unsigned int el; 71 72 el = current_el(); 73 if (el == 1) 74 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 75 else if (el == 2) 76 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 77 else 78 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 79 80 asm volatile("isb"); 81 } 82 83 static inline unsigned long read_mpidr(void) 84 { 85 unsigned long val; 86 87 asm volatile("mrs %0, mpidr_el1" : "=r" (val)); 88 89 return val; 90 } 91 92 #define BSP_COREID 0 93 94 void __asm_flush_dcache_all(void); 95 void __asm_invalidate_dcache_all(void); 96 void __asm_flush_dcache_range(u64 start, u64 end); 97 void __asm_invalidate_tlb_all(void); 98 void __asm_invalidate_icache_all(void); 99 int __asm_flush_l3_cache(void); 100 101 void armv8_switch_to_el2(void); 102 void armv8_switch_to_el1(void); 103 void gic_init(void); 104 void gic_send_sgi(unsigned long sgino); 105 void wait_for_wakeup(void); 106 void protect_secure_region(void); 107 void smp_kick_all_cpus(void); 108 109 void flush_l3_cache(void); 110 111 /* 112 *Issue a hypervisor call in accordance with ARM "SMC Calling convention", 113 * DEN0028A 114 * 115 * @args: input and output arguments 116 * 117 */ 118 void hvc_call(struct pt_regs *args); 119 120 /* 121 *Issue a secure monitor call in accordance with ARM "SMC Calling convention", 122 * DEN0028A 123 * 124 * @args: input and output arguments 125 * 126 */ 127 void smc_call(struct pt_regs *args); 128 129 #endif /* __ASSEMBLY__ */ 130 131 #else /* CONFIG_ARM64 */ 132 133 #ifdef __KERNEL__ 134 135 #define CPU_ARCH_UNKNOWN 0 136 #define CPU_ARCH_ARMv3 1 137 #define CPU_ARCH_ARMv4 2 138 #define CPU_ARCH_ARMv4T 3 139 #define CPU_ARCH_ARMv5 4 140 #define CPU_ARCH_ARMv5T 5 141 #define CPU_ARCH_ARMv5TE 6 142 #define CPU_ARCH_ARMv5TEJ 7 143 #define CPU_ARCH_ARMv6 8 144 #define CPU_ARCH_ARMv7 9 145 146 /* 147 * CR1 bits (CP#15 CR1) 148 */ 149 #define CR_M (1 << 0) /* MMU enable */ 150 #define CR_A (1 << 1) /* Alignment abort enable */ 151 #define CR_C (1 << 2) /* Dcache enable */ 152 #define CR_W (1 << 3) /* Write buffer enable */ 153 #define CR_P (1 << 4) /* 32-bit exception handler */ 154 #define CR_D (1 << 5) /* 32-bit data address range */ 155 #define CR_L (1 << 6) /* Implementation defined */ 156 #define CR_B (1 << 7) /* Big endian */ 157 #define CR_S (1 << 8) /* System MMU protection */ 158 #define CR_R (1 << 9) /* ROM MMU protection */ 159 #define CR_F (1 << 10) /* Implementation defined */ 160 #define CR_Z (1 << 11) /* Implementation defined */ 161 #define CR_I (1 << 12) /* Icache enable */ 162 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 163 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 164 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 165 #define CR_DT (1 << 16) 166 #define CR_IT (1 << 18) 167 #define CR_ST (1 << 19) 168 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 169 #define CR_U (1 << 22) /* Unaligned access operation */ 170 #define CR_XP (1 << 23) /* Extended page tables */ 171 #define CR_VE (1 << 24) /* Vectored interrupts */ 172 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 173 #define CR_TRE (1 << 28) /* TEX remap enable */ 174 #define CR_AFE (1 << 29) /* Access flag enable */ 175 #define CR_TE (1 << 30) /* Thumb exception enable */ 176 177 #ifndef PGTABLE_SIZE 178 #define PGTABLE_SIZE (4096 * 4) 179 #endif 180 181 /* 182 * This is used to ensure the compiler did actually allocate the register we 183 * asked it for some inline assembly sequences. Apparently we can't trust 184 * the compiler from one version to another so a bit of paranoia won't hurt. 185 * This string is meant to be concatenated with the inline asm string and 186 * will cause compilation to stop on mismatch. 187 * (for details, see gcc PR 15089) 188 */ 189 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 190 191 #ifndef __ASSEMBLY__ 192 193 /** 194 * save_boot_params() - Save boot parameters before starting reset sequence 195 * 196 * If you provide this function it will be called immediately U-Boot starts, 197 * both for SPL and U-Boot proper. 198 * 199 * All registers are unchanged from U-Boot entry. No registers need be 200 * preserved. 201 * 202 * This is not a normal C function. There is no stack. Return by branching to 203 * save_boot_params_ret. 204 * 205 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 206 */ 207 208 /** 209 * save_boot_params_ret() - Return from save_boot_params() 210 * 211 * If you provide save_boot_params(), then you should jump back to this 212 * function when done. Try to preserve all registers. 213 * 214 * If your implementation of save_boot_params() is in C then it is acceptable 215 * to simply call save_boot_params_ret() at the end of your function. Since 216 * there is no link register set up, you cannot just exit the function. U-Boot 217 * will return to the (initialised) value of lr, and likely crash/hang. 218 * 219 * If your implementation of save_boot_params() is in assembler then you 220 * should use 'b' or 'bx' to return to save_boot_params_ret. 221 */ 222 void save_boot_params_ret(void); 223 224 #define isb() __asm__ __volatile__ ("" : : : "memory") 225 226 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 227 228 #ifdef __ARM_ARCH_7A__ 229 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 230 #else 231 #define wfi() 232 #endif 233 234 static inline unsigned int get_cr(void) 235 { 236 unsigned int val; 237 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 238 return val; 239 } 240 241 static inline void set_cr(unsigned int val) 242 { 243 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 244 : : "r" (val) : "cc"); 245 isb(); 246 } 247 248 static inline unsigned int get_dacr(void) 249 { 250 unsigned int val; 251 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 252 return val; 253 } 254 255 static inline void set_dacr(unsigned int val) 256 { 257 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 258 : : "r" (val) : "cc"); 259 isb(); 260 } 261 262 #ifdef CONFIG_CPU_V7 263 /* Short-Descriptor Translation Table Level 1 Bits */ 264 #define TTB_SECT_NS_MASK (1 << 19) 265 #define TTB_SECT_NG_MASK (1 << 17) 266 #define TTB_SECT_S_MASK (1 << 16) 267 /* Note: TTB AP bits are set elsewhere */ 268 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 269 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 270 #define TTB_SECT_XN_MASK (1 << 4) 271 #define TTB_SECT_C_MASK (1 << 3) 272 #define TTB_SECT_B_MASK (1 << 2) 273 #define TTB_SECT (2 << 0) 274 275 /* options available for data cache on each page */ 276 enum dcache_option { 277 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, 278 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 279 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 280 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 281 }; 282 #else 283 /* options available for data cache on each page */ 284 enum dcache_option { 285 DCACHE_OFF = 0x12, 286 DCACHE_WRITETHROUGH = 0x1a, 287 DCACHE_WRITEBACK = 0x1e, 288 DCACHE_WRITEALLOC = 0x16, 289 }; 290 #endif 291 292 /* Size of an MMU section */ 293 enum { 294 MMU_SECTION_SHIFT = 20, 295 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 296 }; 297 298 #ifdef CONFIG_CPU_V7 299 /* TTBR0 bits */ 300 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 301 #define TTBR0_RGN_NC (0 << 3) 302 #define TTBR0_RGN_WBWA (1 << 3) 303 #define TTBR0_RGN_WT (2 << 3) 304 #define TTBR0_RGN_WB (3 << 3) 305 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 306 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 307 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 308 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 309 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 310 #endif 311 312 /** 313 * Register an update to the page tables, and flush the TLB 314 * 315 * \param start start address of update in page table 316 * \param stop stop address of update in page table 317 */ 318 void mmu_page_table_flush(unsigned long start, unsigned long stop); 319 320 #endif /* __ASSEMBLY__ */ 321 322 #define arch_align_stack(x) (x) 323 324 #endif /* __KERNEL__ */ 325 326 #endif /* CONFIG_ARM64 */ 327 328 #ifndef __ASSEMBLY__ 329 /** 330 * Change the cache settings for a region. 331 * 332 * \param start start address of memory region to change 333 * \param size size of memory region to change 334 * \param option dcache option to select 335 */ 336 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 337 enum dcache_option option); 338 339 #ifdef CONFIG_SYS_NONCACHED_MEMORY 340 void noncached_init(void); 341 phys_addr_t noncached_alloc(size_t size, size_t align); 342 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 343 344 #endif /* __ASSEMBLY__ */ 345 346 #endif 347