1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #ifdef CONFIG_ARM64 5 6 /* 7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 8 */ 9 #define CR_M (1 << 0) /* MMU enable */ 10 #define CR_A (1 << 1) /* Alignment abort enable */ 11 #define CR_C (1 << 2) /* Dcache enable */ 12 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 13 #define CR_I (1 << 12) /* Icache enable */ 14 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 15 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 16 17 #define PGTABLE_SIZE (0x10000) 18 19 #ifndef __ASSEMBLY__ 20 21 #define isb() \ 22 ({asm volatile( \ 23 "isb" : : : "memory"); \ 24 }) 25 26 #define wfi() \ 27 ({asm volatile( \ 28 "wfi" : : : "memory"); \ 29 }) 30 31 static inline unsigned int current_el(void) 32 { 33 unsigned int el; 34 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 35 return el >> 2; 36 } 37 38 static inline unsigned int get_sctlr(void) 39 { 40 unsigned int el, val; 41 42 el = current_el(); 43 if (el == 1) 44 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 45 else if (el == 2) 46 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 47 else 48 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 49 50 return val; 51 } 52 53 static inline void set_sctlr(unsigned int val) 54 { 55 unsigned int el; 56 57 el = current_el(); 58 if (el == 1) 59 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 60 else if (el == 2) 61 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 62 else 63 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 64 65 asm volatile("isb"); 66 } 67 68 void __asm_flush_dcache_all(void); 69 void __asm_invalidate_dcache_all(void); 70 void __asm_flush_dcache_range(u64 start, u64 end); 71 void __asm_invalidate_tlb_all(void); 72 void __asm_invalidate_icache_all(void); 73 int __asm_flush_l3_cache(void); 74 75 void armv8_switch_to_el2(void); 76 void armv8_switch_to_el1(void); 77 void gic_init(void); 78 void gic_send_sgi(unsigned long sgino); 79 void wait_for_wakeup(void); 80 void protect_secure_region(void); 81 void smp_kick_all_cpus(void); 82 83 void flush_l3_cache(void); 84 85 #endif /* __ASSEMBLY__ */ 86 87 #else /* CONFIG_ARM64 */ 88 89 #ifdef __KERNEL__ 90 91 #define CPU_ARCH_UNKNOWN 0 92 #define CPU_ARCH_ARMv3 1 93 #define CPU_ARCH_ARMv4 2 94 #define CPU_ARCH_ARMv4T 3 95 #define CPU_ARCH_ARMv5 4 96 #define CPU_ARCH_ARMv5T 5 97 #define CPU_ARCH_ARMv5TE 6 98 #define CPU_ARCH_ARMv5TEJ 7 99 #define CPU_ARCH_ARMv6 8 100 #define CPU_ARCH_ARMv7 9 101 102 /* 103 * CR1 bits (CP#15 CR1) 104 */ 105 #define CR_M (1 << 0) /* MMU enable */ 106 #define CR_A (1 << 1) /* Alignment abort enable */ 107 #define CR_C (1 << 2) /* Dcache enable */ 108 #define CR_W (1 << 3) /* Write buffer enable */ 109 #define CR_P (1 << 4) /* 32-bit exception handler */ 110 #define CR_D (1 << 5) /* 32-bit data address range */ 111 #define CR_L (1 << 6) /* Implementation defined */ 112 #define CR_B (1 << 7) /* Big endian */ 113 #define CR_S (1 << 8) /* System MMU protection */ 114 #define CR_R (1 << 9) /* ROM MMU protection */ 115 #define CR_F (1 << 10) /* Implementation defined */ 116 #define CR_Z (1 << 11) /* Implementation defined */ 117 #define CR_I (1 << 12) /* Icache enable */ 118 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 119 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 120 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 121 #define CR_DT (1 << 16) 122 #define CR_IT (1 << 18) 123 #define CR_ST (1 << 19) 124 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 125 #define CR_U (1 << 22) /* Unaligned access operation */ 126 #define CR_XP (1 << 23) /* Extended page tables */ 127 #define CR_VE (1 << 24) /* Vectored interrupts */ 128 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 129 #define CR_TRE (1 << 28) /* TEX remap enable */ 130 #define CR_AFE (1 << 29) /* Access flag enable */ 131 #define CR_TE (1 << 30) /* Thumb exception enable */ 132 133 #define PGTABLE_SIZE (4096 * 4) 134 135 /* 136 * This is used to ensure the compiler did actually allocate the register we 137 * asked it for some inline assembly sequences. Apparently we can't trust 138 * the compiler from one version to another so a bit of paranoia won't hurt. 139 * This string is meant to be concatenated with the inline asm string and 140 * will cause compilation to stop on mismatch. 141 * (for details, see gcc PR 15089) 142 */ 143 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 144 145 #ifndef __ASSEMBLY__ 146 147 /** 148 * save_boot_params() - Save boot parameters before starting reset sequence 149 * 150 * If you provide this function it will be called immediately U-Boot starts, 151 * both for SPL and U-Boot proper. 152 * 153 * All registers are unchanged from U-Boot entry. No registers need be 154 * preserved. 155 * 156 * This is not a normal C function. There is no stack. Return by branching to 157 * save_boot_params_ret. 158 * 159 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 160 */ 161 162 #define isb() __asm__ __volatile__ ("" : : : "memory") 163 164 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 165 166 #ifdef __ARM_ARCH_7A__ 167 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 168 #else 169 #define wfi() 170 #endif 171 172 static inline unsigned int get_cr(void) 173 { 174 unsigned int val; 175 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 176 return val; 177 } 178 179 static inline void set_cr(unsigned int val) 180 { 181 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 182 : : "r" (val) : "cc"); 183 isb(); 184 } 185 186 static inline unsigned int get_dacr(void) 187 { 188 unsigned int val; 189 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 190 return val; 191 } 192 193 static inline void set_dacr(unsigned int val) 194 { 195 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 196 : : "r" (val) : "cc"); 197 isb(); 198 } 199 200 #ifdef CONFIG_ARMV7 201 /* Short-Descriptor Translation Table Level 1 Bits */ 202 #define TTB_SECT_NS_MASK (1 << 19) 203 #define TTB_SECT_NG_MASK (1 << 17) 204 #define TTB_SECT_S_MASK (1 << 16) 205 /* Note: TTB AP bits are set elsewhere */ 206 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 207 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 208 #define TTB_SECT_XN_MASK (1 << 4) 209 #define TTB_SECT_C_MASK (1 << 3) 210 #define TTB_SECT_B_MASK (1 << 2) 211 #define TTB_SECT (2 << 0) 212 213 /* options available for data cache on each page */ 214 enum dcache_option { 215 DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | 216 TTB_SECT_XN_MASK | TTB_SECT, 217 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 218 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 219 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 220 }; 221 #else 222 /* options available for data cache on each page */ 223 enum dcache_option { 224 DCACHE_OFF = 0x12, 225 DCACHE_WRITETHROUGH = 0x1a, 226 DCACHE_WRITEBACK = 0x1e, 227 DCACHE_WRITEALLOC = 0x16, 228 }; 229 #endif 230 231 /* Size of an MMU section */ 232 enum { 233 MMU_SECTION_SHIFT = 20, 234 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 235 }; 236 237 #ifdef CONFIG_ARMV7 238 /* TTBR0 bits */ 239 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 240 #define TTBR0_RGN_NC (0 << 3) 241 #define TTBR0_RGN_WBWA (1 << 3) 242 #define TTBR0_RGN_WT (2 << 3) 243 #define TTBR0_RGN_WB (3 << 3) 244 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 245 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 246 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 247 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 248 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 249 #endif 250 251 /** 252 * Change the cache settings for a region. 253 * 254 * \param start start address of memory region to change 255 * \param size size of memory region to change 256 * \param option dcache option to select 257 */ 258 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 259 enum dcache_option option); 260 261 /** 262 * Register an update to the page tables, and flush the TLB 263 * 264 * \param start start address of update in page table 265 * \param stop stop address of update in page table 266 */ 267 void mmu_page_table_flush(unsigned long start, unsigned long stop); 268 269 #ifdef CONFIG_SYS_NONCACHED_MEMORY 270 void noncached_init(void); 271 phys_addr_t noncached_alloc(size_t size, size_t align); 272 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 273 274 #endif /* __ASSEMBLY__ */ 275 276 #define arch_align_stack(x) (x) 277 278 #endif /* __KERNEL__ */ 279 280 #endif /* CONFIG_ARM64 */ 281 282 #endif 283