1 /*
2  * (C) Copyright 2010
3  * Texas Instruments, <www.ti.com>
4  *
5  * Aneesh V <aneesh@ti.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 #ifndef	_OMAP_COMMON_H_
10 #define	_OMAP_COMMON_H_
11 
12 #ifndef __ASSEMBLY__
13 
14 #include <common.h>
15 
16 #define NUM_SYS_CLKS	7
17 
18 struct prcm_regs {
19 	/* cm1.ckgen */
20 	u32 cm_clksel_core;
21 	u32 cm_clksel_abe;
22 	u32 cm_dll_ctrl;
23 	u32 cm_clkmode_dpll_core;
24 	u32 cm_idlest_dpll_core;
25 	u32 cm_autoidle_dpll_core;
26 	u32 cm_clksel_dpll_core;
27 	u32 cm_div_m2_dpll_core;
28 	u32 cm_div_m3_dpll_core;
29 	u32 cm_div_h11_dpll_core;
30 	u32 cm_div_h12_dpll_core;
31 	u32 cm_div_h13_dpll_core;
32 	u32 cm_div_h14_dpll_core;
33 	u32 cm_div_h21_dpll_core;
34 	u32 cm_div_h24_dpll_core;
35 	u32 cm_ssc_deltamstep_dpll_core;
36 	u32 cm_ssc_modfreqdiv_dpll_core;
37 	u32 cm_emu_override_dpll_core;
38 	u32 cm_div_h22_dpllcore;
39 	u32 cm_div_h23_dpll_core;
40 	u32 cm_clkmode_dpll_mpu;
41 	u32 cm_idlest_dpll_mpu;
42 	u32 cm_autoidle_dpll_mpu;
43 	u32 cm_clksel_dpll_mpu;
44 	u32 cm_div_m2_dpll_mpu;
45 	u32 cm_ssc_deltamstep_dpll_mpu;
46 	u32 cm_ssc_modfreqdiv_dpll_mpu;
47 	u32 cm_bypclk_dpll_mpu;
48 	u32 cm_clkmode_dpll_iva;
49 	u32 cm_idlest_dpll_iva;
50 	u32 cm_autoidle_dpll_iva;
51 	u32 cm_clksel_dpll_iva;
52 	u32 cm_div_h11_dpll_iva;
53 	u32 cm_div_h12_dpll_iva;
54 	u32 cm_ssc_deltamstep_dpll_iva;
55 	u32 cm_ssc_modfreqdiv_dpll_iva;
56 	u32 cm_bypclk_dpll_iva;
57 	u32 cm_clkmode_dpll_abe;
58 	u32 cm_idlest_dpll_abe;
59 	u32 cm_autoidle_dpll_abe;
60 	u32 cm_clksel_dpll_abe;
61 	u32 cm_div_m2_dpll_abe;
62 	u32 cm_div_m3_dpll_abe;
63 	u32 cm_ssc_deltamstep_dpll_abe;
64 	u32 cm_ssc_modfreqdiv_dpll_abe;
65 	u32 cm_clkmode_dpll_ddrphy;
66 	u32 cm_idlest_dpll_ddrphy;
67 	u32 cm_autoidle_dpll_ddrphy;
68 	u32 cm_clksel_dpll_ddrphy;
69 	u32 cm_div_m2_dpll_ddrphy;
70 	u32 cm_div_h11_dpll_ddrphy;
71 	u32 cm_div_h12_dpll_ddrphy;
72 	u32 cm_div_h13_dpll_ddrphy;
73 	u32 cm_ssc_deltamstep_dpll_ddrphy;
74 	u32 cm_clkmode_dpll_dsp;
75 	u32 cm_shadow_freq_config1;
76 	u32 cm_clkmode_dpll_gmac;
77 	u32 cm_mpu_mpu_clkctrl;
78 
79 	/* cm1.dsp */
80 	u32 cm_dsp_clkstctrl;
81 	u32 cm_dsp_dsp_clkctrl;
82 
83 	/* cm1.abe */
84 	u32 cm1_abe_clkstctrl;
85 	u32 cm1_abe_l4abe_clkctrl;
86 	u32 cm1_abe_aess_clkctrl;
87 	u32 cm1_abe_pdm_clkctrl;
88 	u32 cm1_abe_dmic_clkctrl;
89 	u32 cm1_abe_mcasp_clkctrl;
90 	u32 cm1_abe_mcbsp1_clkctrl;
91 	u32 cm1_abe_mcbsp2_clkctrl;
92 	u32 cm1_abe_mcbsp3_clkctrl;
93 	u32 cm1_abe_slimbus_clkctrl;
94 	u32 cm1_abe_timer5_clkctrl;
95 	u32 cm1_abe_timer6_clkctrl;
96 	u32 cm1_abe_timer7_clkctrl;
97 	u32 cm1_abe_timer8_clkctrl;
98 	u32 cm1_abe_wdt3_clkctrl;
99 
100 	/* cm2.ckgen */
101 	u32 cm_clksel_mpu_m3_iss_root;
102 	u32 cm_clksel_usb_60mhz;
103 	u32 cm_scale_fclk;
104 	u32 cm_core_dvfs_perf1;
105 	u32 cm_core_dvfs_perf2;
106 	u32 cm_core_dvfs_perf3;
107 	u32 cm_core_dvfs_perf4;
108 	u32 cm_core_dvfs_current;
109 	u32 cm_iva_dvfs_perf_tesla;
110 	u32 cm_iva_dvfs_perf_ivahd;
111 	u32 cm_iva_dvfs_perf_abe;
112 	u32 cm_iva_dvfs_current;
113 	u32 cm_clkmode_dpll_per;
114 	u32 cm_idlest_dpll_per;
115 	u32 cm_autoidle_dpll_per;
116 	u32 cm_clksel_dpll_per;
117 	u32 cm_div_m2_dpll_per;
118 	u32 cm_div_m3_dpll_per;
119 	u32 cm_div_h11_dpll_per;
120 	u32 cm_div_h12_dpll_per;
121 	u32 cm_div_h13_dpll_per;
122 	u32 cm_div_h14_dpll_per;
123 	u32 cm_ssc_deltamstep_dpll_per;
124 	u32 cm_ssc_modfreqdiv_dpll_per;
125 	u32 cm_emu_override_dpll_per;
126 	u32 cm_clkmode_dpll_usb;
127 	u32 cm_idlest_dpll_usb;
128 	u32 cm_autoidle_dpll_usb;
129 	u32 cm_clksel_dpll_usb;
130 	u32 cm_div_m2_dpll_usb;
131 	u32 cm_ssc_deltamstep_dpll_usb;
132 	u32 cm_ssc_modfreqdiv_dpll_usb;
133 	u32 cm_clkdcoldo_dpll_usb;
134 	u32 cm_clkmode_dpll_pcie_ref;
135 	u32 cm_clkmode_apll_pcie;
136 	u32 cm_idlest_apll_pcie;
137 	u32 cm_div_m2_apll_pcie;
138 	u32 cm_clkvcoldo_apll_pcie;
139 	u32 cm_clkmode_dpll_unipro;
140 	u32 cm_idlest_dpll_unipro;
141 	u32 cm_autoidle_dpll_unipro;
142 	u32 cm_clksel_dpll_unipro;
143 	u32 cm_div_m2_dpll_unipro;
144 	u32 cm_ssc_deltamstep_dpll_unipro;
145 	u32 cm_ssc_modfreqdiv_dpll_unipro;
146 
147 	/* cm2.core */
148 	u32 cm_coreaon_bandgap_clkctrl;
149 	u32 cm_coreaon_io_srcomp_clkctrl;
150 	u32 cm_l3_1_clkstctrl;
151 	u32 cm_l3_1_dynamicdep;
152 	u32 cm_l3_1_l3_1_clkctrl;
153 	u32 cm_l3_2_clkstctrl;
154 	u32 cm_l3_2_dynamicdep;
155 	u32 cm_l3_2_l3_2_clkctrl;
156 	u32 cm_l3_gpmc_clkctrl;
157 	u32 cm_l3_2_ocmc_ram_clkctrl;
158 	u32 cm_mpu_m3_clkstctrl;
159 	u32 cm_mpu_m3_staticdep;
160 	u32 cm_mpu_m3_dynamicdep;
161 	u32 cm_mpu_m3_mpu_m3_clkctrl;
162 	u32 cm_sdma_clkstctrl;
163 	u32 cm_sdma_staticdep;
164 	u32 cm_sdma_dynamicdep;
165 	u32 cm_sdma_sdma_clkctrl;
166 	u32 cm_memif_clkstctrl;
167 	u32 cm_memif_dmm_clkctrl;
168 	u32 cm_memif_emif_fw_clkctrl;
169 	u32 cm_memif_emif_1_clkctrl;
170 	u32 cm_memif_emif_2_clkctrl;
171 	u32 cm_memif_dll_clkctrl;
172 	u32 cm_memif_emif_h1_clkctrl;
173 	u32 cm_memif_emif_h2_clkctrl;
174 	u32 cm_memif_dll_h_clkctrl;
175 	u32 cm_c2c_clkstctrl;
176 	u32 cm_c2c_staticdep;
177 	u32 cm_c2c_dynamicdep;
178 	u32 cm_c2c_sad2d_clkctrl;
179 	u32 cm_c2c_modem_icr_clkctrl;
180 	u32 cm_c2c_sad2d_fw_clkctrl;
181 	u32 cm_l4cfg_clkstctrl;
182 	u32 cm_l4cfg_dynamicdep;
183 	u32 cm_l4cfg_l4_cfg_clkctrl;
184 	u32 cm_l4cfg_hw_sem_clkctrl;
185 	u32 cm_l4cfg_mailbox_clkctrl;
186 	u32 cm_l4cfg_sar_rom_clkctrl;
187 	u32 cm_l3instr_clkstctrl;
188 	u32 cm_l3instr_l3_3_clkctrl;
189 	u32 cm_l3instr_l3_instr_clkctrl;
190 	u32 cm_l3instr_intrconn_wp1_clkctrl;
191 
192 	/* cm2.ivahd */
193 	u32 cm_ivahd_clkstctrl;
194 	u32 cm_ivahd_ivahd_clkctrl;
195 	u32 cm_ivahd_sl2_clkctrl;
196 
197 	/* cm2.cam */
198 	u32 cm_cam_clkstctrl;
199 	u32 cm_cam_iss_clkctrl;
200 	u32 cm_cam_fdif_clkctrl;
201 	u32 cm_cam_vip1_clkctrl;
202 	u32 cm_cam_vip2_clkctrl;
203 	u32 cm_cam_vip3_clkctrl;
204 	u32 cm_cam_lvdsrx_clkctrl;
205 	u32 cm_cam_csi1_clkctrl;
206 	u32 cm_cam_csi2_clkctrl;
207 
208 	/* cm2.dss */
209 	u32 cm_dss_clkstctrl;
210 	u32 cm_dss_dss_clkctrl;
211 
212 	/* cm2.sgx */
213 	u32 cm_sgx_clkstctrl;
214 	u32 cm_sgx_sgx_clkctrl;
215 
216 	/* cm2.l3init */
217 	u32 cm_l3init_clkstctrl;
218 
219 	/* cm2.l3init */
220 	u32 cm_l3init_hsmmc1_clkctrl;
221 	u32 cm_l3init_hsmmc2_clkctrl;
222 	u32 cm_l3init_hsi_clkctrl;
223 	u32 cm_l3init_hsusbhost_clkctrl;
224 	u32 cm_l3init_hsusbotg_clkctrl;
225 	u32 cm_l3init_hsusbtll_clkctrl;
226 	u32 cm_l3init_p1500_clkctrl;
227 	u32 cm_l3init_fsusb_clkctrl;
228 	u32 cm_l3init_ocp2scp1_clkctrl;
229 
230 	u32 prm_irqstatus_mpu_2;
231 
232 	/* cm2.l4per */
233 	u32 cm_l4per_clkstctrl;
234 	u32 cm_l4per_dynamicdep;
235 	u32 cm_l4per_adc_clkctrl;
236 	u32 cm_l4per_gptimer10_clkctrl;
237 	u32 cm_l4per_gptimer11_clkctrl;
238 	u32 cm_l4per_gptimer2_clkctrl;
239 	u32 cm_l4per_gptimer3_clkctrl;
240 	u32 cm_l4per_gptimer4_clkctrl;
241 	u32 cm_l4per_gptimer9_clkctrl;
242 	u32 cm_l4per_elm_clkctrl;
243 	u32 cm_l4per_gpio2_clkctrl;
244 	u32 cm_l4per_gpio3_clkctrl;
245 	u32 cm_l4per_gpio4_clkctrl;
246 	u32 cm_l4per_gpio5_clkctrl;
247 	u32 cm_l4per_gpio6_clkctrl;
248 	u32 cm_l4per_hdq1w_clkctrl;
249 	u32 cm_l4per_hecc1_clkctrl;
250 	u32 cm_l4per_hecc2_clkctrl;
251 	u32 cm_l4per_i2c1_clkctrl;
252 	u32 cm_l4per_i2c2_clkctrl;
253 	u32 cm_l4per_i2c3_clkctrl;
254 	u32 cm_l4per_i2c4_clkctrl;
255 	u32 cm_l4per_l4per_clkctrl;
256 	u32 cm_l4per_mcasp2_clkctrl;
257 	u32 cm_l4per_mcasp3_clkctrl;
258 	u32 cm_l4per_mgate_clkctrl;
259 	u32 cm_l4per_mcspi1_clkctrl;
260 	u32 cm_l4per_mcspi2_clkctrl;
261 	u32 cm_l4per_mcspi3_clkctrl;
262 	u32 cm_l4per_mcspi4_clkctrl;
263 	u32 cm_l4per_gpio7_clkctrl;
264 	u32 cm_l4per_gpio8_clkctrl;
265 	u32 cm_l4per_mmcsd3_clkctrl;
266 	u32 cm_l4per_mmcsd4_clkctrl;
267 	u32 cm_l4per_msprohg_clkctrl;
268 	u32 cm_l4per_slimbus2_clkctrl;
269 	u32 cm_l4per_qspi_clkctrl;
270 	u32 cm_l4per_uart1_clkctrl;
271 	u32 cm_l4per_uart2_clkctrl;
272 	u32 cm_l4per_uart3_clkctrl;
273 	u32 cm_l4per_uart4_clkctrl;
274 	u32 cm_l4per_mmcsd5_clkctrl;
275 	u32 cm_l4per_i2c5_clkctrl;
276 	u32 cm_l4per_uart5_clkctrl;
277 	u32 cm_l4per_uart6_clkctrl;
278 	u32 cm_l4sec_clkstctrl;
279 	u32 cm_l4sec_staticdep;
280 	u32 cm_l4sec_dynamicdep;
281 	u32 cm_l4sec_aes1_clkctrl;
282 	u32 cm_l4sec_aes2_clkctrl;
283 	u32 cm_l4sec_des3des_clkctrl;
284 	u32 cm_l4sec_pkaeip29_clkctrl;
285 	u32 cm_l4sec_rng_clkctrl;
286 	u32 cm_l4sec_sha2md51_clkctrl;
287 	u32 cm_l4sec_cryptodma_clkctrl;
288 
289 	/* l4 wkup regs */
290 	u32 cm_abe_pll_ref_clksel;
291 	u32 cm_sys_clksel;
292 	u32 cm_abe_pll_sys_clksel;
293 	u32 cm_wkup_clkstctrl;
294 	u32 cm_wkup_l4wkup_clkctrl;
295 	u32 cm_wkup_wdtimer1_clkctrl;
296 	u32 cm_wkup_wdtimer2_clkctrl;
297 	u32 cm_wkup_gpio1_clkctrl;
298 	u32 cm_wkup_gptimer1_clkctrl;
299 	u32 cm_wkup_gptimer12_clkctrl;
300 	u32 cm_wkup_synctimer_clkctrl;
301 	u32 cm_wkup_usim_clkctrl;
302 	u32 cm_wkup_sarram_clkctrl;
303 	u32 cm_wkup_keyboard_clkctrl;
304 	u32 cm_wkup_rtc_clkctrl;
305 	u32 cm_wkup_bandgap_clkctrl;
306 	u32 cm_wkupaon_scrm_clkctrl;
307 	u32 cm_wkupaon_io_srcomp_clkctrl;
308 	u32 prm_rstctrl;
309 	u32 prm_rstst;
310 	u32 prm_rsttime;
311 	u32 prm_vc_val_bypass;
312 	u32 prm_vc_cfg_i2c_mode;
313 	u32 prm_vc_cfg_i2c_clk;
314 	u32 prm_abbldo_mpu_setup;
315 	u32 prm_abbldo_mpu_ctrl;
316 
317 	u32 cm_div_m4_dpll_core;
318 	u32 cm_div_m5_dpll_core;
319 	u32 cm_div_m6_dpll_core;
320 	u32 cm_div_m7_dpll_core;
321 	u32 cm_div_m4_dpll_iva;
322 	u32 cm_div_m5_dpll_iva;
323 	u32 cm_div_m4_dpll_ddrphy;
324 	u32 cm_div_m5_dpll_ddrphy;
325 	u32 cm_div_m6_dpll_ddrphy;
326 	u32 cm_div_m4_dpll_per;
327 	u32 cm_div_m5_dpll_per;
328 	u32 cm_div_m6_dpll_per;
329 	u32 cm_div_m7_dpll_per;
330 	u32 cm_l3instr_intrconn_wp1_clkct;
331 	u32 cm_l3init_usbphy_clkctrl;
332 	u32 cm_l4per_mcbsp4_clkctrl;
333 	u32 prm_vc_cfg_channel;
334 
335 	/* SCRM stuff, used by some boards */
336 	u32 scrm_auxclk0;
337 	u32 scrm_auxclk1;
338 
339 	/* GMAC Clk Ctrl */
340 	u32 cm_gmac_gmac_clkctrl;
341 	u32 cm_gmac_clkstctrl;
342 };
343 
344 struct omap_sys_ctrl_regs {
345 	u32 control_status;
346 	u32 control_core_mac_id_0_lo;
347 	u32 control_core_mac_id_0_hi;
348 	u32 control_core_mac_id_1_lo;
349 	u32 control_core_mac_id_1_hi;
350 	u32 control_std_fuse_opp_vdd_mpu_2;
351 	u32 control_core_mmr_lock1;
352 	u32 control_core_mmr_lock2;
353 	u32 control_core_mmr_lock3;
354 	u32 control_core_mmr_lock4;
355 	u32 control_core_mmr_lock5;
356 	u32 control_core_control_io1;
357 	u32 control_core_control_io2;
358 	u32 control_id_code;
359 	u32 control_std_fuse_opp_bgap;
360 	u32 control_ldosram_iva_voltage_ctrl;
361 	u32 control_ldosram_mpu_voltage_ctrl;
362 	u32 control_ldosram_core_voltage_ctrl;
363 	u32 control_usbotghs_ctrl;
364 	u32 control_padconf_core_base;
365 	u32 control_paconf_global;
366 	u32 control_paconf_mode;
367 	u32 control_smart1io_padconf_0;
368 	u32 control_smart1io_padconf_1;
369 	u32 control_smart1io_padconf_2;
370 	u32 control_smart2io_padconf_0;
371 	u32 control_smart2io_padconf_1;
372 	u32 control_smart2io_padconf_2;
373 	u32 control_smart3io_padconf_0;
374 	u32 control_smart3io_padconf_1;
375 	u32 control_pbias;
376 	u32 control_i2c_0;
377 	u32 control_camera_rx;
378 	u32 control_hdmi_tx_phy;
379 	u32 control_uniportm;
380 	u32 control_dsiphy;
381 	u32 control_mcbsplp;
382 	u32 control_usb2phycore;
383 	u32 control_hdmi_1;
384 	u32 control_hsi;
385 	u32 control_ddr3ch1_0;
386 	u32 control_ddr3ch2_0;
387 	u32 control_ddrch1_0;
388 	u32 control_ddrch1_1;
389 	u32 control_ddrch2_0;
390 	u32 control_ddrch2_1;
391 	u32 control_lpddr2ch1_0;
392 	u32 control_lpddr2ch1_1;
393 	u32 control_ddrio_0;
394 	u32 control_ddrio_1;
395 	u32 control_ddrio_2;
396 	u32 control_ddr_control_ext_0;
397 	u32 control_lpddr2io1_0;
398 	u32 control_lpddr2io1_1;
399 	u32 control_lpddr2io1_2;
400 	u32 control_lpddr2io1_3;
401 	u32 control_lpddr2io2_0;
402 	u32 control_lpddr2io2_1;
403 	u32 control_lpddr2io2_2;
404 	u32 control_lpddr2io2_3;
405 	u32 control_hyst_1;
406 	u32 control_usbb_hsic_control;
407 	u32 control_c2c;
408 	u32 control_core_control_spare_rw;
409 	u32 control_core_control_spare_r;
410 	u32 control_core_control_spare_r_c0;
411 	u32 control_srcomp_north_side;
412 	u32 control_srcomp_south_side;
413 	u32 control_srcomp_east_side;
414 	u32 control_srcomp_west_side;
415 	u32 control_srcomp_code_latch;
416 	u32 control_pbiaslite;
417 	u32 control_port_emif1_sdram_config;
418 	u32 control_port_emif1_lpddr2_nvm_config;
419 	u32 control_port_emif2_sdram_config;
420 	u32 control_emif1_sdram_config_ext;
421 	u32 control_emif2_sdram_config_ext;
422 	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
423 	u32 control_smart1nopmio_padconf_0;
424 	u32 control_smart1nopmio_padconf_1;
425 	u32 control_padconf_mode;
426 	u32 control_xtal_oscillator;
427 	u32 control_i2c_2;
428 	u32 control_ckobuffer;
429 	u32 control_wkup_control_spare_rw;
430 	u32 control_wkup_control_spare_r;
431 	u32 control_wkup_control_spare_r_c0;
432 	u32 control_srcomp_east_side_wkup;
433 	u32 control_efuse_1;
434 	u32 control_efuse_2;
435 	u32 control_efuse_3;
436 	u32 control_efuse_4;
437 	u32 control_efuse_5;
438 	u32 control_efuse_6;
439 	u32 control_efuse_7;
440 	u32 control_efuse_8;
441 	u32 control_efuse_9;
442 	u32 control_efuse_10;
443 	u32 control_efuse_11;
444 	u32 control_efuse_12;
445 	u32 control_efuse_13;
446 	u32 control_padconf_wkup_base;
447 };
448 
449 struct dpll_params {
450 	u32 m;
451 	u32 n;
452 	s8 m2;
453 	s8 m3;
454 	s8 m4_h11;
455 	s8 m5_h12;
456 	s8 m6_h13;
457 	s8 m7_h14;
458 	s8 h21;
459 	s8 h22;
460 	s8 h23;
461 	s8 h24;
462 };
463 
464 struct dpll_regs {
465 	u32 cm_clkmode_dpll;
466 	u32 cm_idlest_dpll;
467 	u32 cm_autoidle_dpll;
468 	u32 cm_clksel_dpll;
469 	u32 cm_div_m2_dpll;
470 	u32 cm_div_m3_dpll;
471 	u32 cm_div_m4_h11_dpll;
472 	u32 cm_div_m5_h12_dpll;
473 	u32 cm_div_m6_h13_dpll;
474 	u32 cm_div_m7_h14_dpll;
475 	u32 reserved[2];
476 	u32 cm_div_h21_dpll;
477 	u32 cm_div_h22_dpll;
478 	u32 cm_div_h23_dpll;
479 	u32 cm_div_h24_dpll;
480 };
481 
482 struct dplls {
483 	const struct dpll_params *mpu;
484 	const struct dpll_params *core;
485 	const struct dpll_params *per;
486 	const struct dpll_params *abe;
487 	const struct dpll_params *iva;
488 	const struct dpll_params *usb;
489 	const struct dpll_params *ddr;
490 	const struct dpll_params *gmac;
491 };
492 
493 struct pmic_data {
494 	u32 base_offset;
495 	u32 step;
496 	u32 start_code;
497 	unsigned gpio;
498 	int gpio_en;
499 	u32 i2c_slave_addr;
500 	void (*pmic_bus_init)(void);
501 	int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
502 };
503 
504 /**
505  * struct volts_efuse_data - efuse definition for voltage
506  * @reg:	register address for efuse
507  * @reg_bits:	Number of bits in a register address, mandatory.
508  */
509 struct volts_efuse_data {
510 	u32 reg;
511 	u8 reg_bits;
512 };
513 
514 struct volts {
515 	u32 value;
516 	u32 addr;
517 	struct volts_efuse_data efuse;
518 	struct pmic_data *pmic;
519 };
520 
521 struct vcores_data {
522 	struct volts mpu;
523 	struct volts core;
524 	struct volts mm;
525 	struct volts gpu;
526 	struct volts eve;
527 	struct volts iva;
528 };
529 
530 extern struct prcm_regs const **prcm;
531 extern struct prcm_regs const omap5_es1_prcm;
532 extern struct prcm_regs const omap5_es2_prcm;
533 extern struct prcm_regs const omap4_prcm;
534 extern struct prcm_regs const dra7xx_prcm;
535 extern struct dplls const **dplls_data;
536 extern struct vcores_data const **omap_vcores;
537 extern const u32 sys_clk_array[8];
538 extern struct omap_sys_ctrl_regs const **ctrl;
539 extern struct omap_sys_ctrl_regs const omap4_ctrl;
540 extern struct omap_sys_ctrl_regs const omap5_ctrl;
541 extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
542 
543 void hw_data_init(void);
544 
545 const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
546 const struct dpll_params *get_core_dpll_params(struct dplls const *);
547 const struct dpll_params *get_per_dpll_params(struct dplls const *);
548 const struct dpll_params *get_iva_dpll_params(struct dplls const *);
549 const struct dpll_params *get_usb_dpll_params(struct dplls const *);
550 const struct dpll_params *get_abe_dpll_params(struct dplls const *);
551 
552 void do_enable_clocks(u32 const *clk_domains,
553 		      u32 const *clk_modules_hw_auto,
554 		      u32 const *clk_modules_explicit_en,
555 		      u8 wait_for_enable);
556 
557 void setup_post_dividers(u32 const base,
558 			const struct dpll_params *params);
559 u32 omap_ddr_clk(void);
560 u32 get_sys_clk_index(void);
561 void enable_basic_clocks(void);
562 void enable_basic_uboot_clocks(void);
563 void enable_non_essential_clocks(void);
564 void scale_vcores(struct vcores_data const *);
565 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
566 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
567 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
568 	       u32 txdone, u32 txdone_mask, u32 opp);
569 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
570 
571 /* HW Init Context */
572 #define OMAP_INIT_CONTEXT_SPL			0
573 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
574 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
575 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
576 
577 /* ABB */
578 #define OMAP_ABB_NOMINAL_OPP		0
579 #define OMAP_ABB_FAST_OPP		1
580 #define OMAP_ABB_SLOW_OPP		3
581 #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK		(0x1 << 0)
582 #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK		(0x1 << 1)
583 #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK		(0x1 << 2)
584 #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK		(0x1 << 6)
585 #define OMAP_ABB_SETUP_SR2EN_MASK			(0x1 << 0)
586 #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK		(0x1 << 2)
587 #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK		(0x1 << 1)
588 #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK		(0xff << 8)
589 
590 static inline u32 omap_revision(void)
591 {
592 	extern u32 *const omap_si_rev;
593 	return *omap_si_rev;
594 }
595 
596 #define OMAP54xx	0x54000000
597 
598 static inline u8 is_omap54xx(void)
599 {
600 	extern u32 *const omap_si_rev;
601 	return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
602 }
603 #endif
604 
605 /*
606  * silicon revisions.
607  * Moving this to common, so that most of code can be moved to common,
608  * directories.
609  */
610 
611 /* omap4 */
612 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
613 #define OMAP4430_ES1_0	0x44300100
614 #define OMAP4430_ES2_0	0x44300200
615 #define OMAP4430_ES2_1	0x44300210
616 #define OMAP4430_ES2_2	0x44300220
617 #define OMAP4430_ES2_3	0x44300230
618 #define OMAP4460_ES1_0	0x44600100
619 #define OMAP4460_ES1_1	0x44600110
620 #define OMAP4470_ES1_0	0x44700100
621 
622 /* omap5 */
623 #define OMAP5430_SILICON_ID_INVALID	0
624 #define OMAP5430_ES1_0	0x54300100
625 #define OMAP5432_ES1_0	0x54320100
626 #define OMAP5430_ES2_0  0x54300200
627 #define OMAP5432_ES2_0  0x54320200
628 
629 /* DRA7XX */
630 #define DRA752_ES1_0	0x07520100
631 
632 /*
633  * SRAM scratch space entries
634  */
635 #define OMAP_SRAM_SCRATCH_OMAP_REV	SRAM_SCRATCH_SPACE_ADDR
636 #define OMAP_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
637 #define OMAP_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
638 #define OMAP_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
639 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
640 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
641 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
642 #define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
643 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
644 #define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x28)
645 
646 #endif /* _OMAP_COMMON_H_ */
647