1 /* 2 * include/asm-arm/macro.h 3 * 4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __ASM_ARM_MACRO_H__ 10 #define __ASM_ARM_MACRO_H__ 11 12 #ifdef CONFIG_ARM64 13 #include <asm/system.h> 14 #endif 15 16 #ifdef __ASSEMBLY__ 17 18 /* 19 * These macros provide a convenient way to write 8, 16 and 32 bit data 20 * to any address. 21 * Registers r4 and r5 are used, any data in these registers are 22 * overwritten by the macros. 23 * The macros are valid for any ARM architecture, they do not implement 24 * any memory barriers so caution is recommended when using these when the 25 * caches are enabled or on a multi-core system. 26 */ 27 28 .macro write32, addr, data 29 ldr r4, =\addr 30 ldr r5, =\data 31 str r5, [r4] 32 .endm 33 34 .macro write16, addr, data 35 ldr r4, =\addr 36 ldrh r5, =\data 37 strh r5, [r4] 38 .endm 39 40 .macro write8, addr, data 41 ldr r4, =\addr 42 ldrb r5, =\data 43 strb r5, [r4] 44 .endm 45 46 /* 47 * This macro generates a loop that can be used for delays in the code. 48 * Register r4 is used, any data in this register is overwritten by the 49 * macro. 50 * The macro is valid for any ARM architeture. The actual time spent in the 51 * loop will vary from CPU to CPU though. 52 */ 53 54 .macro wait_timer, time 55 ldr r4, =\time 56 1: 57 nop 58 subs r4, r4, #1 59 bcs 1b 60 .endm 61 62 #ifdef CONFIG_ARM64 63 /* 64 * Register aliases. 65 */ 66 lr .req x30 67 68 /* 69 * Branch according to exception level 70 */ 71 .macro switch_el, xreg, el3_label, el2_label, el1_label 72 mrs \xreg, CurrentEL 73 cmp \xreg, 0xc 74 b.eq \el3_label 75 cmp \xreg, 0x8 76 b.eq \el2_label 77 cmp \xreg, 0x4 78 b.eq \el1_label 79 .endm 80 81 /* 82 * Branch if current processor is a Cortex-A57 core. 83 */ 84 .macro branch_if_a57_core, xreg, a57_label 85 mrs \xreg, midr_el1 86 lsr \xreg, \xreg, #4 87 and \xreg, \xreg, #0x00000FFF 88 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */ 89 b.eq \a57_label 90 .endm 91 92 /* 93 * Branch if current processor is a Cortex-A53 core. 94 */ 95 .macro branch_if_a53_core, xreg, a53_label 96 mrs \xreg, midr_el1 97 lsr \xreg, \xreg, #4 98 and \xreg, \xreg, #0x00000FFF 99 cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */ 100 b.eq \a53_label 101 .endm 102 103 /* 104 * Branch if current processor is a slave, 105 * choose processor with all zero affinity value as the master. 106 */ 107 .macro branch_if_slave, xreg, slave_label 108 #ifdef CONFIG_ARMV8_MULTIENTRY 109 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ 110 mrs \xreg, mpidr_el1 111 tst \xreg, #0xff /* Test Affinity 0 */ 112 b.ne \slave_label 113 lsr \xreg, \xreg, #8 114 tst \xreg, #0xff /* Test Affinity 1 */ 115 b.ne \slave_label 116 lsr \xreg, \xreg, #8 117 tst \xreg, #0xff /* Test Affinity 2 */ 118 b.ne \slave_label 119 lsr \xreg, \xreg, #16 120 tst \xreg, #0xff /* Test Affinity 3 */ 121 b.ne \slave_label 122 #endif 123 .endm 124 125 /* 126 * Branch if current processor is a master, 127 * choose processor with all zero affinity value as the master. 128 */ 129 .macro branch_if_master, xreg1, xreg2, master_label 130 #ifdef CONFIG_ARMV8_MULTIENTRY 131 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ 132 mrs \xreg1, mpidr_el1 133 lsr \xreg2, \xreg1, #32 134 lsl \xreg2, \xreg2, #32 135 lsl \xreg1, \xreg1, #40 136 lsr \xreg1, \xreg1, #40 137 orr \xreg1, \xreg1, \xreg2 138 cbz \xreg1, \master_label 139 #else 140 b \master_label 141 #endif 142 .endm 143 144 /* 145 * Switch from EL3 to EL2 for ARMv8 146 * @ep: kernel entry point 147 * @flag: The execution state flag for lower exception 148 * level, ES_TO_AARCH64 or ES_TO_AARCH32 149 * @tmp: temporary register 150 * 151 * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr. 152 * For loading 64-bit OS, x0 is physical address to the FDT blob. 153 * They will be passed to the guest. 154 */ 155 .macro armv8_switch_to_el2_m, ep, flag, tmp 156 msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ 157 mov \tmp, #CPTR_EL2_RES1 158 msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */ 159 160 /* Initialize Generic Timers */ 161 msr cntvoff_el2, xzr 162 163 /* Initialize SCTLR_EL2 164 * 165 * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1 166 * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) + 167 * EE,WXN,I,SA,C,A,M to 0 168 */ 169 ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\ 170 SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\ 171 SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\ 172 SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS) 173 msr sctlr_el2, \tmp 174 175 mov \tmp, sp 176 msr sp_el2, \tmp /* Migrate SP */ 177 mrs \tmp, vbar_el3 178 msr vbar_el2, \tmp /* Migrate VBAR */ 179 180 /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */ 181 cmp \flag, #ES_TO_AARCH32 182 b.eq 1f 183 184 /* 185 * The next lower exception level is AArch64, 64bit EL2 | HCE | 186 * RES1 (Bits[5:4]) | Non-secure EL0/EL1. 187 * and the SMD depends on requirements. 188 */ 189 #ifdef CONFIG_ARMV8_PSCI 190 ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ 191 SCR_EL3_RES1 | SCR_EL3_NS_EN) 192 #else 193 ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ 194 SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ 195 SCR_EL3_NS_EN) 196 #endif 197 msr scr_el3, \tmp 198 199 /* Return to the EL2_SP2 mode from EL3 */ 200 ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\ 201 SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ 202 SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H) 203 msr spsr_el3, \tmp 204 msr elr_el3, \ep 205 eret 206 207 1: 208 /* 209 * The next lower exception level is AArch32, 32bit EL2 | HCE | 210 * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1. 211 */ 212 ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\ 213 SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ 214 SCR_EL3_NS_EN) 215 msr scr_el3, \tmp 216 217 /* Return to AArch32 Hypervisor mode */ 218 ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\ 219 SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ 220 SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\ 221 SPSR_EL_M_HYP) 222 msr spsr_el3, \tmp 223 msr elr_el3, \ep 224 eret 225 .endm 226 227 /* 228 * Switch from EL2 to EL1 for ARMv8 229 * @ep: kernel entry point 230 * @flag: The execution state flag for lower exception 231 * level, ES_TO_AARCH64 or ES_TO_AARCH32 232 * @tmp: temporary register 233 * 234 * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr. 235 * For loading 64-bit OS, x0 is physical address to the FDT blob. 236 * They will be passed to the guest. 237 */ 238 .macro armv8_switch_to_el1_m, ep, flag, tmp 239 /* Initialize Generic Timers */ 240 mrs \tmp, cnthctl_el2 241 /* Enable EL1 access to timers */ 242 orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\ 243 CNTHCTL_EL2_EL1PCTEN_EN) 244 msr cnthctl_el2, \tmp 245 msr cntvoff_el2, xzr 246 247 /* Initilize MPID/MPIDR registers */ 248 mrs \tmp, midr_el1 249 msr vpidr_el2, \tmp 250 mrs \tmp, mpidr_el1 251 msr vmpidr_el2, \tmp 252 253 /* Disable coprocessor traps */ 254 mov \tmp, #CPTR_EL2_RES1 255 msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */ 256 msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */ 257 mov \tmp, #CPACR_EL1_FPEN_EN 258 msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */ 259 260 /* SCTLR_EL1 initialization 261 * 262 * setting RES1 bits (29,28,23,22,20,11) to 1 263 * and RES0 bits (31,30,27,21,17,13,10,6) + 264 * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD, 265 * CP15BEN,SA0,SA,C,A,M to 0 266 */ 267 ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\ 268 SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\ 269 SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\ 270 SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\ 271 SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\ 272 SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\ 273 SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\ 274 SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\ 275 SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS) 276 msr sctlr_el1, \tmp 277 278 mov \tmp, sp 279 msr sp_el1, \tmp /* Migrate SP */ 280 mrs \tmp, vbar_el2 281 msr vbar_el1, \tmp /* Migrate VBAR */ 282 283 /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */ 284 cmp \flag, #ES_TO_AARCH32 285 b.eq 1f 286 287 /* Initialize HCR_EL2 */ 288 ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) 289 msr hcr_el2, \tmp 290 291 /* Return to the EL1_SP1 mode from EL2 */ 292 ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\ 293 SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ 294 SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H) 295 msr spsr_el2, \tmp 296 msr elr_el2, \ep 297 eret 298 299 1: 300 /* Initialize HCR_EL2 */ 301 ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS) 302 msr hcr_el2, \tmp 303 304 /* Return to AArch32 Supervisor mode from EL2 */ 305 ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\ 306 SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ 307 SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\ 308 SPSR_EL_M_SVC) 309 msr spsr_el2, \tmp 310 msr elr_el2, \ep 311 eret 312 .endm 313 314 #if defined(CONFIG_GICV3) 315 .macro gic_wait_for_interrupt_m xreg1 316 0 : wfi 317 mrs \xreg1, ICC_IAR1_EL1 318 msr ICC_EOIR1_EL1, \xreg1 319 cbnz \xreg1, 0b 320 .endm 321 #elif defined(CONFIG_GICV2) 322 .macro gic_wait_for_interrupt_m xreg1, wreg2 323 0 : wfi 324 ldr \wreg2, [\xreg1, GICC_AIAR] 325 str \wreg2, [\xreg1, GICC_AEOIR] 326 and \wreg2, \wreg2, #0x3ff 327 cbnz \wreg2, 0b 328 .endm 329 #endif 330 331 #endif /* CONFIG_ARM64 */ 332 333 #endif /* __ASSEMBLY__ */ 334 #endif /* __ASM_ARM_MACRO_H__ */ 335