1 /*
2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ASM_ARCH_SYSTEM_COUNTER_H
8 #define _ASM_ARCH_SYSTEM_COUNTER_H
9 
10 /* System Counter */
11 struct sctr_regs {
12 	u32 cntcr;
13 	u32 cntsr;
14 	u32 cntcv1;
15 	u32 cntcv2;
16 	u32 resv1[4];
17 	u32 cntfid0;
18 	u32 cntfid1;
19 	u32 cntfid2;
20 	u32 resv2[1001];
21 	u32 counterid[1];
22 };
23 
24 #define SC_CNTCR_ENABLE		(1 << 0)
25 #define SC_CNTCR_HDBG		(1 << 1)
26 #define SC_CNTCR_FREQ0		(1 << 8)
27 #define SC_CNTCR_FREQ1		(1 << 9)
28 
29 #endif
30