1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 5 */ 6 7 #ifndef _SYS_PROTO_H_ 8 #define _SYS_PROTO_H_ 9 10 #include <asm/io.h> 11 #include <asm/mach-imx/regs-common.h> 12 #include <common.h> 13 #include "../arch-imx/cpu.h" 14 15 #define soc_rev() (get_cpu_rev() & 0xFF) 16 #define is_soc_rev(rev) (soc_rev() == rev) 17 18 /* returns MXC_CPU_ value */ 19 #define cpu_type(rev) (((rev) >> 12) & 0xff) 20 #define soc_type(rev) (((rev) >> 12) & 0xf0) 21 /* both macros return/take MXC_CPU_ constants */ 22 #define get_cpu_type() (cpu_type(get_cpu_rev())) 23 #define get_soc_type() (soc_type(get_cpu_rev())) 24 #define is_cpu_type(cpu) (get_cpu_type() == cpu) 25 #define is_soc_type(soc) (get_soc_type() == soc) 26 27 #define is_mx6() (is_soc_type(MXC_SOC_MX6)) 28 #define is_mx7() (is_soc_type(MXC_SOC_MX7)) 29 #define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) 30 #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 31 32 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 33 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 34 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) 35 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) 36 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) 37 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) 38 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) 39 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) 40 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) 41 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) 42 43 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 44 45 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 46 47 #ifdef CONFIG_MX6 48 #define IMX6_SRC_GPR10_BMODE BIT(28) 49 50 #define IMX6_BMODE_MASK GENMASK(7, 0) 51 #define IMX6_BMODE_SHIFT 4 52 #define IMX6_BMODE_EMI_MASK BIT(3) 53 #define IMX6_BMODE_EMI_SHIFT 3 54 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) 55 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 56 57 enum imx6_bmode_serial_rom { 58 IMX6_BMODE_ECSPI1, 59 IMX6_BMODE_ECSPI2, 60 IMX6_BMODE_ECSPI3, 61 IMX6_BMODE_ECSPI4, 62 IMX6_BMODE_ECSPI5, 63 IMX6_BMODE_I2C1, 64 IMX6_BMODE_I2C2, 65 IMX6_BMODE_I2C3, 66 }; 67 68 enum imx6_bmode_emi { 69 IMX6_BMODE_ONENAND, 70 IMX6_BMODE_NOR, 71 }; 72 73 enum imx6_bmode { 74 IMX6_BMODE_EMI, 75 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 76 IMX6_BMODE_QSPI, 77 IMX6_BMODE_RESERVED, 78 #else 79 IMX6_BMODE_RESERVED, 80 IMX6_BMODE_SATA, 81 #endif 82 IMX6_BMODE_SERIAL_ROM, 83 IMX6_BMODE_SD, 84 IMX6_BMODE_ESD, 85 IMX6_BMODE_MMC, 86 IMX6_BMODE_EMMC, 87 IMX6_BMODE_NAND_MIN, 88 IMX6_BMODE_NAND_MAX = 0xf, 89 }; 90 91 static inline u8 imx6_is_bmode_from_gpr9(void) 92 { 93 return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE; 94 } 95 96 u32 imx6_src_get_boot_mode(void); 97 void gpr_init(void); 98 99 #endif /* CONFIG_MX6 */ 100 101 u32 get_nr_cpus(void); 102 u32 get_cpu_rev(void); 103 u32 get_cpu_speed_grade_hz(void); 104 u32 get_cpu_temp_grade(int *minc, int *maxc); 105 const char *get_imx_type(u32 imxtype); 106 u32 imx_ddr_size(void); 107 void sdelay(unsigned long); 108 void set_chipselect_size(int const); 109 110 void init_aips(void); 111 void init_src(void); 112 void init_snvs(void); 113 void imx_wdog_disable_powerdown(void); 114 115 int board_mmc_get_env_dev(int devno); 116 117 int nxp_board_rev(void); 118 char nxp_board_rev_string(void); 119 120 /* 121 * Initializes on-chip ethernet controllers. 122 * to override, implement board_eth_init() 123 */ 124 int fecmxc_initialize(bd_t *bis); 125 u32 get_ahb_clk(void); 126 u32 get_periph_clk(void); 127 128 void lcdif_power_down(void); 129 130 int mxs_reset_block(struct mxs_register_32 *reg); 131 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); 132 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); 133 134 unsigned long call_imx_sip(unsigned long id, unsigned long reg0, 135 unsigned long reg1, unsigned long reg2); 136 #endif 137