1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
4  *
5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6  * on behalf of DENX Software Engineering GmbH
7  *
8  * Based on code from LTIB:
9  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10  */
11 
12 #ifndef __IMX_REGS_LCDIF_H__
13 #define __IMX_REGS_LCDIF_H__
14 
15 #ifndef	__ASSEMBLY__
16 #include <asm/mach-imx/regs-common.h>
17 
18 struct mxs_lcdif_regs {
19 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
20 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
21 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
22 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
23 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
24 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
25 	defined(CONFIG_MX8M)
26 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
27 #endif
28 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
29 	mxs_reg_32(hw_lcdif_cur_buf)		/* 0x30/0x40 */
30 	mxs_reg_32(hw_lcdif_next_buf)		/* 0x40/0x50 */
31 
32 #if defined(CONFIG_MX23)
33 	uint32_t	reserved1[4];
34 #endif
35 
36 	mxs_reg_32(hw_lcdif_timing)		/* 0x60 */
37 	mxs_reg_32(hw_lcdif_vdctrl0)		/* 0x70 */
38 	mxs_reg_32(hw_lcdif_vdctrl1)		/* 0x80 */
39 	mxs_reg_32(hw_lcdif_vdctrl2)		/* 0x90 */
40 	mxs_reg_32(hw_lcdif_vdctrl3)		/* 0xa0 */
41 	mxs_reg_32(hw_lcdif_vdctrl4)		/* 0xb0 */
42 	mxs_reg_32(hw_lcdif_dvictrl0)		/* 0xc0 */
43 	mxs_reg_32(hw_lcdif_dvictrl1)		/* 0xd0 */
44 	mxs_reg_32(hw_lcdif_dvictrl2)		/* 0xe0 */
45 	mxs_reg_32(hw_lcdif_dvictrl3)		/* 0xf0 */
46 	mxs_reg_32(hw_lcdif_dvictrl4)		/* 0x100 */
47 	mxs_reg_32(hw_lcdif_csc_coeffctrl0)	/* 0x110 */
48 	mxs_reg_32(hw_lcdif_csc_coeffctrl1)	/* 0x120 */
49 	mxs_reg_32(hw_lcdif_csc_coeffctrl2)	/* 0x130 */
50 	mxs_reg_32(hw_lcdif_csc_coeffctrl3)	/* 0x140 */
51 	mxs_reg_32(hw_lcdif_csc_coeffctrl4)	/* 0x150 */
52 	mxs_reg_32(hw_lcdif_csc_offset)	/* 0x160 */
53 	mxs_reg_32(hw_lcdif_csc_limit)		/* 0x170 */
54 
55 #if defined(CONFIG_MX23)
56 	uint32_t	reserved2[12];
57 #endif
58 	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
59 	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
60 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
61 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
62 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
63 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
64 	defined(CONFIG_MX8M)
65 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
66 #endif
67 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
68 	mxs_reg_32(hw_lcdif_version)		/* 0x1e0/0x1c0 */
69 	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
70 	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
71 	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
72 #if defined(CONFIG_MX6SX) || \
73 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
74 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
75 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
76 	defined(CONFIG_MX8M)
77 	mxs_reg_32(hw_lcdif_thres)
78 	mxs_reg_32(hw_lcdif_as_ctrl)
79 	mxs_reg_32(hw_lcdif_as_buf)
80 	mxs_reg_32(hw_lcdif_as_next_buf)
81 	mxs_reg_32(hw_lcdif_as_clrkeylow)
82 	mxs_reg_32(hw_lcdif_as_clrkeyhigh)
83 	mxs_reg_32(hw_lcdif_as_sync_delay)
84 	mxs_reg_32(hw_lcdif_as_debug3)
85 	mxs_reg_32(hw_lcdif_as_debug4)
86 	mxs_reg_32(hw_lcdif_as_debug5)
87 #endif
88 };
89 #endif
90 
91 #define	LCDIF_CTRL_SFTRST					(1 << 31)
92 #define	LCDIF_CTRL_CLKGATE					(1 << 30)
93 #define	LCDIF_CTRL_YCBCR422_INPUT				(1 << 29)
94 #define	LCDIF_CTRL_READ_WRITEB					(1 << 28)
95 #define	LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE				(1 << 27)
96 #define	LCDIF_CTRL_DATA_SHIFT_DIR				(1 << 26)
97 #define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK				(0x1f << 21)
98 #define	LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET			21
99 #define	LCDIF_CTRL_DVI_MODE					(1 << 20)
100 #define	LCDIF_CTRL_BYPASS_COUNT					(1 << 19)
101 #define	LCDIF_CTRL_VSYNC_MODE					(1 << 18)
102 #define	LCDIF_CTRL_DOTCLK_MODE					(1 << 17)
103 #define	LCDIF_CTRL_DATA_SELECT					(1 << 16)
104 #define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK			(0x3 << 14)
105 #define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET			14
106 #define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK			(0x3 << 12)
107 #define	LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET			12
108 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK			(0x3 << 10)
109 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET			10
110 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT			(0 << 10)
111 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT			(1 << 10)
112 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT			(2 << 10)
113 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT			(3 << 10)
114 #define	LCDIF_CTRL_WORD_LENGTH_MASK				(0x3 << 8)
115 #define	LCDIF_CTRL_WORD_LENGTH_OFFSET				8
116 #define	LCDIF_CTRL_WORD_LENGTH_16BIT				(0 << 8)
117 #define	LCDIF_CTRL_WORD_LENGTH_8BIT				(1 << 8)
118 #define	LCDIF_CTRL_WORD_LENGTH_18BIT				(2 << 8)
119 #define	LCDIF_CTRL_WORD_LENGTH_24BIT				(3 << 8)
120 #define	LCDIF_CTRL_RGB_TO_YCBCR422_CSC				(1 << 7)
121 #define	LCDIF_CTRL_LCDIF_MASTER					(1 << 5)
122 #define	LCDIF_CTRL_DATA_FORMAT_16_BIT				(1 << 3)
123 #define	LCDIF_CTRL_DATA_FORMAT_18_BIT				(1 << 2)
124 #define	LCDIF_CTRL_DATA_FORMAT_24_BIT				(1 << 1)
125 #define	LCDIF_CTRL_RUN						(1 << 0)
126 
127 #define	LCDIF_CTRL1_COMBINE_MPU_WR_STRB				(1 << 27)
128 #define	LCDIF_CTRL1_BM_ERROR_IRQ_EN				(1 << 26)
129 #define	LCDIF_CTRL1_BM_ERROR_IRQ				(1 << 25)
130 #define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW			(1 << 24)
131 #define	LCDIF_CTRL1_INTERLACE_FIELDS				(1 << 23)
132 #define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD		(1 << 22)
133 #define	LCDIF_CTRL1_FIFO_CLEAR					(1 << 21)
134 #define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS			(1 << 20)
135 #define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK			(0xf << 16)
136 #define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET			16
137 #define	LCDIF_CTRL1_OVERFLOW_IRQ_EN				(1 << 15)
138 #define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN				(1 << 14)
139 #define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN			(1 << 13)
140 #define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN				(1 << 12)
141 #define	LCDIF_CTRL1_OVERFLOW_IRQ				(1 << 11)
142 #define	LCDIF_CTRL1_UNDERFLOW_IRQ				(1 << 10)
143 #define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ				(1 << 9)
144 #define	LCDIF_CTRL1_VSYNC_EDGE_IRQ				(1 << 8)
145 #define	LCDIF_CTRL1_BUSY_ENABLE					(1 << 2)
146 #define	LCDIF_CTRL1_MODE86					(1 << 1)
147 #define	LCDIF_CTRL1_RESET					(1 << 0)
148 
149 #define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK			(0x7 << 21)
150 #define	LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET			21
151 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1			(0x0 << 21)
152 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2			(0x1 << 21)
153 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4			(0x2 << 21)
154 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8			(0x3 << 21)
155 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16			(0x4 << 21)
156 #define	LCDIF_CTRL2_BURST_LEN_8					(1 << 20)
157 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK			(0x7 << 16)
158 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET			16
159 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_RGB			(0x0 << 16)
160 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_RBG			(0x1 << 16)
161 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_GBR			(0x2 << 16)
162 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_GRB			(0x3 << 16)
163 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_BRG			(0x4 << 16)
164 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_BGR			(0x5 << 16)
165 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK			(0x7 << 12)
166 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET			12
167 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB			(0x0 << 12)
168 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG			(0x1 << 12)
169 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR			(0x2 << 12)
170 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB			(0x3 << 12)
171 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG			(0x4 << 12)
172 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR			(0x5 << 12)
173 #define	LCDIF_CTRL2_READ_PACK_DIR				(1 << 10)
174 #define	LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT		(1 << 9)
175 #define	LCDIF_CTRL2_READ_MODE_6_BIT_INPUT			(1 << 8)
176 #define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK		(0x7 << 4)
177 #define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET	4
178 #define	LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK			(0x7 << 1)
179 #define	LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET			1
180 
181 #define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK			(0xffff << 16)
182 #define	LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET			16
183 #define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK			(0xffff << 0)
184 #define	LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET			0
185 
186 #define	LCDIF_CUR_BUF_ADDR_MASK					0xffffffff
187 #define	LCDIF_CUR_BUF_ADDR_OFFSET				0
188 
189 #define	LCDIF_NEXT_BUF_ADDR_MASK				0xffffffff
190 #define	LCDIF_NEXT_BUF_ADDR_OFFSET				0
191 
192 #define	LCDIF_TIMING_CMD_HOLD_MASK				(0xff << 24)
193 #define	LCDIF_TIMING_CMD_HOLD_OFFSET				24
194 #define	LCDIF_TIMING_CMD_SETUP_MASK				(0xff << 16)
195 #define	LCDIF_TIMING_CMD_SETUP_OFFSET				16
196 #define	LCDIF_TIMING_DATA_HOLD_MASK				(0xff << 8)
197 #define	LCDIF_TIMING_DATA_HOLD_OFFSET				8
198 #define	LCDIF_TIMING_DATA_SETUP_MASK				(0xff << 0)
199 #define	LCDIF_TIMING_DATA_SETUP_OFFSET				0
200 
201 #define	LCDIF_VDCTRL0_VSYNC_OEB					(1 << 29)
202 #define	LCDIF_VDCTRL0_ENABLE_PRESENT				(1 << 28)
203 #define	LCDIF_VDCTRL0_VSYNC_POL					(1 << 27)
204 #define	LCDIF_VDCTRL0_HSYNC_POL					(1 << 26)
205 #define	LCDIF_VDCTRL0_DOTCLK_POL				(1 << 25)
206 #define	LCDIF_VDCTRL0_ENABLE_POL				(1 << 24)
207 #define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT				(1 << 21)
208 #define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT			(1 << 20)
209 #define	LCDIF_VDCTRL0_HALF_LINE					(1 << 19)
210 #define	LCDIF_VDCTRL0_HALF_LINE_MODE				(1 << 18)
211 #define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK			0x3ffff
212 #define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET			0
213 
214 #define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
215 #define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
216 
217 #if defined(CONFIG_MX23)
218 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0xff << 24)
219 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			24
220 #else
221 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
222 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
223 #endif
224 #define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
225 #define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
226 
227 #define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS				(1 << 29)
228 #define	LCDIF_VDCTRL3_VSYNC_ONLY				(1 << 28)
229 #define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK			(0xfff << 16)
230 #define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET		16
231 #define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK			(0xffff << 0)
232 #define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET			0
233 
234 #define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK			(0x7 << 29)
235 #define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET			29
236 #define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON				(1 << 18)
237 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
238 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
239 
240 #endif /* __IMX_REGS_LCDIF_H__ */
241