1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2552a848eSStefano Babic /* 3552a848eSStefano Babic * Freescale i.MXS Register Accessors 4552a848eSStefano Babic * 5552a848eSStefano Babic * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6552a848eSStefano Babic * on behalf of DENX Software Engineering GmbH 7552a848eSStefano Babic */ 8552a848eSStefano Babic 9552a848eSStefano Babic #ifndef __MXS_REGS_COMMON_H__ 10552a848eSStefano Babic #define __MXS_REGS_COMMON_H__ 11552a848eSStefano Babic 12552a848eSStefano Babic #include <linux/types.h> 13552a848eSStefano Babic 14552a848eSStefano Babic /* 15552a848eSStefano Babic * The i.MXS has interesting feature when it comes to register access. There 16552a848eSStefano Babic * are four kinds of access to one particular register. Those are: 17552a848eSStefano Babic * 18552a848eSStefano Babic * 1) Common read/write access. To use this mode, just write to the address of 19552a848eSStefano Babic * the register. 20552a848eSStefano Babic * 2) Set bits only access. To set bits, write which bits you want to set to the 21552a848eSStefano Babic * address of the register + 0x4. 22552a848eSStefano Babic * 3) Clear bits only access. To clear bits, write which bits you want to clear 23552a848eSStefano Babic * to the address of the register + 0x8. 24552a848eSStefano Babic * 4) Toggle bits only access. To toggle bits, write which bits you want to 25552a848eSStefano Babic * toggle to the address of the register + 0xc. 26552a848eSStefano Babic * 27552a848eSStefano Babic * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits 28552a848eSStefano Babic * can be set/cleared by pure write as in access type 1, some need to be 29552a848eSStefano Babic * explicitly set/cleared by using access type 2-3. 30552a848eSStefano Babic * 31552a848eSStefano Babic * The following macros and structures allow the user to either access the 32552a848eSStefano Babic * register in all aforementioned modes (by accessing reg_name, reg_name_set, 33552a848eSStefano Babic * reg_name_clr, reg_name_tog) or pass the register structure further into 34552a848eSStefano Babic * various functions with correct type information (by accessing reg_name_reg). 35552a848eSStefano Babic * 36552a848eSStefano Babic */ 37552a848eSStefano Babic 38552a848eSStefano Babic #define __mxs_reg_8(name) \ 39552a848eSStefano Babic uint8_t name[4]; \ 40552a848eSStefano Babic uint8_t name##_set[4]; \ 41552a848eSStefano Babic uint8_t name##_clr[4]; \ 42552a848eSStefano Babic uint8_t name##_tog[4]; \ 43552a848eSStefano Babic 44552a848eSStefano Babic #define __mxs_reg_32(name) \ 45552a848eSStefano Babic uint32_t name; \ 46552a848eSStefano Babic uint32_t name##_set; \ 47552a848eSStefano Babic uint32_t name##_clr; \ 48552a848eSStefano Babic uint32_t name##_tog; 49552a848eSStefano Babic 50552a848eSStefano Babic struct mxs_register_8 { 51552a848eSStefano Babic __mxs_reg_8(reg) 52552a848eSStefano Babic }; 53552a848eSStefano Babic 54552a848eSStefano Babic struct mxs_register_32 { 55552a848eSStefano Babic __mxs_reg_32(reg) 56552a848eSStefano Babic }; 57552a848eSStefano Babic 58552a848eSStefano Babic #define mxs_reg_8(name) \ 59552a848eSStefano Babic union { \ 60552a848eSStefano Babic struct { __mxs_reg_8(name) }; \ 61552a848eSStefano Babic struct mxs_register_8 name##_reg; \ 62552a848eSStefano Babic }; 63552a848eSStefano Babic 64552a848eSStefano Babic #define mxs_reg_32(name) \ 65552a848eSStefano Babic union { \ 66552a848eSStefano Babic struct { __mxs_reg_32(name) }; \ 67552a848eSStefano Babic struct mxs_register_32 name##_reg; \ 68552a848eSStefano Babic }; 69552a848eSStefano Babic 70552a848eSStefano Babic #endif /* __MXS_REGS_COMMON_H__ */ 71