1*552a848eSStefano Babic /* 2*552a848eSStefano Babic * Freescale i.MXS Register Accessors 3*552a848eSStefano Babic * 4*552a848eSStefano Babic * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*552a848eSStefano Babic * on behalf of DENX Software Engineering GmbH 6*552a848eSStefano Babic * 7*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+ 8*552a848eSStefano Babic */ 9*552a848eSStefano Babic 10*552a848eSStefano Babic #ifndef __MXS_REGS_COMMON_H__ 11*552a848eSStefano Babic #define __MXS_REGS_COMMON_H__ 12*552a848eSStefano Babic 13*552a848eSStefano Babic #include <linux/types.h> 14*552a848eSStefano Babic 15*552a848eSStefano Babic /* 16*552a848eSStefano Babic * The i.MXS has interesting feature when it comes to register access. There 17*552a848eSStefano Babic * are four kinds of access to one particular register. Those are: 18*552a848eSStefano Babic * 19*552a848eSStefano Babic * 1) Common read/write access. To use this mode, just write to the address of 20*552a848eSStefano Babic * the register. 21*552a848eSStefano Babic * 2) Set bits only access. To set bits, write which bits you want to set to the 22*552a848eSStefano Babic * address of the register + 0x4. 23*552a848eSStefano Babic * 3) Clear bits only access. To clear bits, write which bits you want to clear 24*552a848eSStefano Babic * to the address of the register + 0x8. 25*552a848eSStefano Babic * 4) Toggle bits only access. To toggle bits, write which bits you want to 26*552a848eSStefano Babic * toggle to the address of the register + 0xc. 27*552a848eSStefano Babic * 28*552a848eSStefano Babic * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits 29*552a848eSStefano Babic * can be set/cleared by pure write as in access type 1, some need to be 30*552a848eSStefano Babic * explicitly set/cleared by using access type 2-3. 31*552a848eSStefano Babic * 32*552a848eSStefano Babic * The following macros and structures allow the user to either access the 33*552a848eSStefano Babic * register in all aforementioned modes (by accessing reg_name, reg_name_set, 34*552a848eSStefano Babic * reg_name_clr, reg_name_tog) or pass the register structure further into 35*552a848eSStefano Babic * various functions with correct type information (by accessing reg_name_reg). 36*552a848eSStefano Babic * 37*552a848eSStefano Babic */ 38*552a848eSStefano Babic 39*552a848eSStefano Babic #define __mxs_reg_8(name) \ 40*552a848eSStefano Babic uint8_t name[4]; \ 41*552a848eSStefano Babic uint8_t name##_set[4]; \ 42*552a848eSStefano Babic uint8_t name##_clr[4]; \ 43*552a848eSStefano Babic uint8_t name##_tog[4]; \ 44*552a848eSStefano Babic 45*552a848eSStefano Babic #define __mxs_reg_32(name) \ 46*552a848eSStefano Babic uint32_t name; \ 47*552a848eSStefano Babic uint32_t name##_set; \ 48*552a848eSStefano Babic uint32_t name##_clr; \ 49*552a848eSStefano Babic uint32_t name##_tog; 50*552a848eSStefano Babic 51*552a848eSStefano Babic struct mxs_register_8 { 52*552a848eSStefano Babic __mxs_reg_8(reg) 53*552a848eSStefano Babic }; 54*552a848eSStefano Babic 55*552a848eSStefano Babic struct mxs_register_32 { 56*552a848eSStefano Babic __mxs_reg_32(reg) 57*552a848eSStefano Babic }; 58*552a848eSStefano Babic 59*552a848eSStefano Babic #define mxs_reg_8(name) \ 60*552a848eSStefano Babic union { \ 61*552a848eSStefano Babic struct { __mxs_reg_8(name) }; \ 62*552a848eSStefano Babic struct mxs_register_8 name##_reg; \ 63*552a848eSStefano Babic }; 64*552a848eSStefano Babic 65*552a848eSStefano Babic #define mxs_reg_32(name) \ 66*552a848eSStefano Babic union { \ 67*552a848eSStefano Babic struct { __mxs_reg_32(name) }; \ 68*552a848eSStefano Babic struct mxs_register_32 name##_reg; \ 69*552a848eSStefano Babic }; 70*552a848eSStefano Babic 71*552a848eSStefano Babic #endif /* __MXS_REGS_COMMON_H__ */ 72