1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Based on Linux i.MX iomux-v3.h file:
4  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
5  *			<armlinux@phytec.de>
6  *
7  * Copyright (C) 2011 Freescale Semiconductor, Inc.
8  */
9 
10 #ifndef __MACH_IOMUX_V3_H__
11 #define __MACH_IOMUX_V3_H__
12 
13 #include <common.h>
14 
15 /*
16  *	build IOMUX_PAD structure
17  *
18  * This iomux scheme is based around pads, which are the physical balls
19  * on the processor.
20  *
21  * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
22  *   things like driving strength and pullup/pulldown.
23  * - Each pad can have but not necessarily does have an output routing register
24  *   (IOMUXC_SW_MUX_CTL_PAD_x).
25  * - Each pad can have but not necessarily does have an input routing register
26  *   (IOMUXC_x_SELECT_INPUT)
27  *
28  * The three register sets do not have a fixed offset to each other,
29  * hence we order this table by pad control registers (which all pads
30  * have) and put the optional i/o routing registers into additional
31  * fields.
32  *
33  * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
34  * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
35  *
36  * IOMUX/PAD Bit field definitions
37  *
38  * MUX_CTRL_OFS:	    0..11 (12)
39  * PAD_CTRL_OFS:	   12..23 (12)
40  * SEL_INPUT_OFS:	   24..35 (12)
41  * MUX_MODE + SION + LPSR: 36..41  (6)
42  * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
43  * SEL_INP:		   60..63  (4)
44 */
45 
46 typedef u64 iomux_v3_cfg_t;
47 
48 #define MUX_CTRL_OFS_SHIFT	0
49 #define MUX_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
50 #define MUX_PAD_CTRL_OFS_SHIFT	12
51 #define MUX_PAD_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
52 	MUX_PAD_CTRL_OFS_SHIFT)
53 #define MUX_SEL_INPUT_OFS_SHIFT	24
54 #define MUX_SEL_INPUT_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
55 	MUX_SEL_INPUT_OFS_SHIFT)
56 
57 #define MUX_MODE_SHIFT		36
58 #define MUX_MODE_MASK		((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
59 #define MUX_PAD_CTRL_SHIFT	42
60 #define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
61 #define MUX_SEL_INPUT_SHIFT	60
62 #define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
63 
64 #define MUX_MODE_SION		((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
65 	MUX_MODE_SHIFT)
66 #define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
67 
68 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
69 		sel_input, pad_ctrl)					\
70 	(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |	\
71 	((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |	\
72 	((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |	\
73 	((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |	\
74 	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|	\
75 	((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
76 
77 #define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
78 					MUX_PAD_CTRL(pad))
79 
80 #define __NA_			0x000
81 #define NO_MUX_I		0
82 #define NO_PAD_I		0
83 
84 #define NO_PAD_CTRL		(1 << 17)
85 
86 #define IOMUX_CONFIG_LPSR       0x20
87 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
88 				MUX_MODE_SHIFT)
89 #ifdef CONFIG_MX8M
90 #define PAD_CTL_DSE0		(0x0 << 0)
91 #define PAD_CTL_DSE1		(0x1 << 0)
92 #define PAD_CTL_DSE2		(0x2 << 0)
93 #define PAD_CTL_DSE3		(0x3 << 0)
94 #define PAD_CTL_DSE4		(0x4 << 0)
95 #define PAD_CTL_DSE5		(0x5 << 0)
96 #define PAD_CTL_DSE6		(0x6 << 0)
97 #define PAD_CTL_DSE7		(0x7 << 0)
98 
99 #define PAD_CTL_FSEL0		(0x0 << 3)
100 #define PAD_CTL_FSEL1		(0x1 << 3)
101 #define PAD_CTL_FSEL2		(0x2 << 3)
102 #define PAD_CTL_FSEL3		(0x3 << 3)
103 
104 #define PAD_CTL_ODE		(0x1 << 5)
105 #define PAD_CTL_PUE		(0x1 << 6)
106 #define PAD_CTL_HYS		(0x1 << 7)
107 #define PAD_CTL_LVTTL		(0x1 << 8)
108 
109 #elif defined CONFIG_MX7
110 
111 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
112 
113 #define PAD_CTL_DSE_1P8V_140OHM   (0x0<<0)
114 #define PAD_CTL_DSE_1P8V_35OHM    (0x1<<0)
115 #define PAD_CTL_DSE_1P8V_70OHM    (0x2<<0)
116 #define PAD_CTL_DSE_1P8V_23OHM    (0x3<<0)
117 
118 #define PAD_CTL_DSE_3P3V_196OHM   (0x0<<0)
119 #define PAD_CTL_DSE_3P3V_49OHM    (0x1<<0)
120 #define PAD_CTL_DSE_3P3V_98OHM    (0x2<<0)
121 #define PAD_CTL_DSE_3P3V_32OHM    (0x3<<0)
122 
123 #define PAD_CTL_SRE_FAST     (0 << 2)
124 #define PAD_CTL_SRE_SLOW     (0x1 << 2)
125 
126 #define PAD_CTL_HYS       (0x1 << 3)
127 #define PAD_CTL_PUE       (0x1 << 4)
128 
129 #define PAD_CTL_PUS_PD100KOHM  ((0x0 << 5) | PAD_CTL_PUE)
130 #define PAD_CTL_PUS_PU5KOHM    ((0x1 << 5) | PAD_CTL_PUE)
131 #define PAD_CTL_PUS_PU47KOHM   ((0x2 << 5) | PAD_CTL_PUE)
132 #define PAD_CTL_PUS_PU100KOHM  ((0x3 << 5) | PAD_CTL_PUE)
133 
134 #else
135 
136 #ifdef CONFIG_MX6
137 
138 #define PAD_CTL_HYS		(1 << 16)
139 
140 #define PAD_CTL_PUS_100K_DOWN	(0 << 14 | PAD_CTL_PUE)
141 #define PAD_CTL_PUS_47K_UP	(1 << 14 | PAD_CTL_PUE)
142 #define PAD_CTL_PUS_100K_UP	(2 << 14 | PAD_CTL_PUE)
143 #define PAD_CTL_PUS_22K_UP	(3 << 14 | PAD_CTL_PUE)
144 #define PAD_CTL_PUE		(1 << 13 | PAD_CTL_PKE)
145 #define PAD_CTL_PKE		(1 << 12)
146 
147 #define PAD_CTL_ODE		(1 << 11)
148 
149 #if defined(CONFIG_MX6SL)
150 #define PAD_CTL_SPEED_LOW	(1 << 6)
151 #else
152 #define PAD_CTL_SPEED_LOW	(0 << 6)
153 #endif
154 #define PAD_CTL_SPEED_MED	(2 << 6)
155 #define PAD_CTL_SPEED_HIGH	(3 << 6)
156 
157 #define PAD_CTL_DSE_DISABLE	(0 << 3)
158 #define PAD_CTL_DSE_240ohm	(1 << 3)
159 #define PAD_CTL_DSE_120ohm	(2 << 3)
160 #define PAD_CTL_DSE_80ohm	(3 << 3)
161 #define PAD_CTL_DSE_60ohm	(4 << 3)
162 #define PAD_CTL_DSE_48ohm	(5 << 3)
163 #define PAD_CTL_DSE_40ohm	(6 << 3)
164 #define PAD_CTL_DSE_34ohm	(7 << 3)
165 
166 #define PAD_CTL_DSE_260ohm	(1 << 3)
167 #define PAD_CTL_DSE_130ohm	(2 << 3)
168 #define PAD_CTL_DSE_88ohm	(3 << 3)
169 #define PAD_CTL_DSE_65ohm	(4 << 3)
170 #define PAD_CTL_DSE_52ohm	(5 << 3)
171 #define PAD_CTL_DSE_43ohm	(6 << 3)
172 #define PAD_CTL_DSE_37ohm	(7 << 3)
173 
174 /* i.MX6SL/SLL */
175 #define PAD_CTL_LVE		(1 << 1)
176 #define PAD_CTL_LVE_BIT		(1 << 22)
177 
178 /* i.MX6SLL */
179 #define PAD_CTL_IPD_BIT		(1 << 27)
180 
181 #elif defined(CONFIG_VF610)
182 
183 #define PAD_MUX_MODE_SHIFT	20
184 
185 #define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
186 
187 #define PAD_CTL_SPEED_MED	(1 << 12)
188 #define PAD_CTL_SPEED_HIGH	(3 << 12)
189 
190 #define PAD_CTL_SRE		(1 << 11)
191 
192 #define PAD_CTL_ODE		(1 << 10)
193 
194 #define PAD_CTL_DSE_150ohm	(1 << 6)
195 #define PAD_CTL_DSE_75ohm	(2 << 6)
196 #define PAD_CTL_DSE_50ohm	(3 << 6)
197 #define PAD_CTL_DSE_37ohm	(4 << 6)
198 #define PAD_CTL_DSE_30ohm	(5 << 6)
199 #define PAD_CTL_DSE_25ohm	(6 << 6)
200 #define PAD_CTL_DSE_20ohm	(7 << 6)
201 
202 #define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
203 #define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
204 #define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
205 #define PAD_CTL_PKE		(1 << 3)
206 #define PAD_CTL_PUE		(1 << 2 | PAD_CTL_PKE)
207 
208 #define PAD_CTL_OBE_IBE_ENABLE	(3 << 0)
209 #define PAD_CTL_OBE_ENABLE	(1 << 1)
210 #define PAD_CTL_IBE_ENABLE	(1 << 0)
211 
212 #else
213 
214 #define PAD_CTL_DVS		(1 << 13)
215 #define PAD_CTL_INPUT_DDR	(1 << 9)
216 #define PAD_CTL_HYS		(1 << 8)
217 
218 #define PAD_CTL_PKE		(1 << 7)
219 #define PAD_CTL_PUE		(1 << 6 | PAD_CTL_PKE)
220 #define PAD_CTL_PUS_100K_DOWN	(0 << 4 | PAD_CTL_PUE)
221 #define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
222 #define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
223 #define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
224 
225 #define PAD_CTL_ODE		(1 << 3)
226 
227 #define PAD_CTL_DSE_LOW		(0 << 1)
228 #define PAD_CTL_DSE_MED		(1 << 1)
229 #define PAD_CTL_DSE_HIGH	(2 << 1)
230 #define PAD_CTL_DSE_MAX		(3 << 1)
231 
232 #endif
233 
234 #define PAD_CTL_SRE_SLOW	(0 << 0)
235 #define PAD_CTL_SRE_FAST	(1 << 0)
236 
237 #endif
238 
239 #define IOMUX_CONFIG_SION	0x10
240 
241 #define GPIO_PIN_MASK		0x1f
242 #define GPIO_PORT_SHIFT		5
243 #define GPIO_PORT_MASK		(0x7 << GPIO_PORT_SHIFT)
244 #define GPIO_PORTA		(0 << GPIO_PORT_SHIFT)
245 #define GPIO_PORTB		(1 << GPIO_PORT_SHIFT)
246 #define GPIO_PORTC		(2 << GPIO_PORT_SHIFT)
247 #define GPIO_PORTD		(3 << GPIO_PORT_SHIFT)
248 #define GPIO_PORTE		(4 << GPIO_PORT_SHIFT)
249 #define GPIO_PORTF		(5 << GPIO_PORT_SHIFT)
250 
251 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
252 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
253 				     unsigned count);
254 /*
255 * Set bits for general purpose registers
256 */
257 void imx_iomux_set_gpr_register(int group, int start_bit,
258 					 int num_bits, int value);
259 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
260 void imx_iomux_gpio_set_direction(unsigned int gpio,
261 				unsigned int direction);
262 void imx_iomux_gpio_get_function(unsigned int gpio,
263 				u32 *gpio_state);
264 #endif
265 
266 /* macros for declaring and using pinmux array */
267 #if defined(CONFIG_MX6QDL)
268 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
269 #define SETUP_IOMUX_PAD(def)					\
270 if (is_mx6dq() || is_mx6dqp()) {				\
271 	imx_iomux_v3_setup_pad(MX6Q_##def);			\
272 } else {							\
273 	imx_iomux_v3_setup_pad(MX6DL_##def);			\
274 }
275 #define SETUP_IOMUX_PADS(x)					\
276 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
277 #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
278 #define IOMUX_PADS(x) MX6Q_##x
279 #define SETUP_IOMUX_PAD(def)					\
280 	imx_iomux_v3_setup_pad(MX6Q_##def);
281 #define SETUP_IOMUX_PADS(x)					\
282 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
283 #elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
284 #define IOMUX_PADS(x) MX6_##x
285 #define SETUP_IOMUX_PAD(def)					\
286 	imx_iomux_v3_setup_pad(MX6_##def);
287 #define SETUP_IOMUX_PADS(x)					\
288 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
289 #else
290 #define IOMUX_PADS(x) MX6DL_##x
291 #define SETUP_IOMUX_PAD(def)					\
292 	imx_iomux_v3_setup_pad(MX6DL_##def);
293 #define SETUP_IOMUX_PADS(x)					\
294 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
295 #endif
296 
297 #endif	/* __MACH_IOMUX_V3_H__*/
298