xref: /openbmc/u-boot/arch/arm/include/asm/mach-imx/hab.h (revision 704744f8)
1 /*
2  * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:    GPL-2.0+
5  *
6 */
7 
8 #ifndef __SECURE_MX6Q_H__
9 #define __SECURE_MX6Q_H__
10 
11 #include <linux/types.h>
12 #include <linux/compiler.h>
13 
14 /*
15  * IVT header definitions
16  * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
17  * Rev. 0, 03/2017
18  * Section : 6.7.1.1
19  */
20 #define IVT_HEADER_MAGIC	0xD1
21 #define IVT_TOTAL_LENGTH	0x20
22 #define IVT_HEADER_V1		0x40
23 #define IVT_HEADER_V2		0x41
24 
25 struct __packed ivt_header {
26 	uint8_t		magic;
27 	uint16_t	length;
28 	uint8_t		version;
29 };
30 
31 struct ivt {
32 	struct ivt_header hdr;	/* IVT header above */
33 	uint32_t entry;		/* Absolute address of first instruction */
34 	uint32_t reserved1;	/* Reserved should be zero */
35 	uint32_t dcd;		/* Absolute address of the image DCD */
36 	uint32_t boot;		/* Absolute address of the boot data */
37 	uint32_t self;		/* Absolute address of the IVT */
38 	uint32_t csf;		/* Absolute address of the CSF */
39 	uint32_t reserved2;	/* Reserved should be zero */
40 };
41 
42 struct __packed hab_hdr {
43 	u8 tag;              /* Tag field */
44 	u8 len[2];           /* Length field in bytes (big-endian) */
45 	u8 par;              /* Parameters field */
46 };
47 
48 /* -------- start of HAB API updates ------------*/
49 /* The following are taken from HAB4 SIS */
50 
51 /* Status definitions */
52 enum hab_status {
53 	HAB_STS_ANY = 0x00,
54 	HAB_FAILURE = 0x33,
55 	HAB_WARNING = 0x69,
56 	HAB_SUCCESS = 0xf0
57 };
58 
59 /* Security Configuration definitions */
60 enum hab_config {
61 	HAB_CFG_RETURN = 0x33,	/* < Field Return IC */
62 	HAB_CFG_OPEN = 0xf0,	/* < Non-secure IC */
63 	HAB_CFG_CLOSED = 0xcc	/* < Secure IC */
64 };
65 
66 /* State definitions */
67 enum hab_state {
68 	HAB_STATE_INITIAL = 0x33,	/* Initialising state (transitory) */
69 	HAB_STATE_CHECK = 0x55,		/* Check state (non-secure) */
70 	HAB_STATE_NONSECURE = 0x66,	/* Non-secure state */
71 	HAB_STATE_TRUSTED = 0x99,	/* Trusted state */
72 	HAB_STATE_SECURE = 0xaa,	/* Secure state */
73 	HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
74 	HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
75 	HAB_STATE_NONE = 0xf0,		/* No security state machine */
76 	HAB_STATE_MAX
77 };
78 
79 enum hab_reason {
80 	HAB_RSN_ANY = 0x00,			/* Match any reason */
81 	HAB_ENG_FAIL = 0x30,		/* Engine failure */
82 	HAB_INV_ADDRESS = 0x22,		/* Invalid address: access denied */
83 	HAB_INV_ASSERTION = 0x0c,   /* Invalid assertion */
84 	HAB_INV_CALL = 0x28,		/* Function called out of sequence */
85 	HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
86 	HAB_INV_COMMAND = 0x06,     /* Invalid command: command malformed */
87 	HAB_INV_CSF = 0x11,			/* Invalid csf */
88 	HAB_INV_DCD = 0x27,			/* Invalid dcd */
89 	HAB_INV_INDEX = 0x0f,		/* Invalid index: access denied */
90 	HAB_INV_IVT = 0x05,			/* Invalid ivt */
91 	HAB_INV_KEY = 0x1d,			/* Invalid key */
92 	HAB_INV_RETURN = 0x1e,		/* Failed callback function */
93 	HAB_INV_SIGNATURE = 0x18,   /* Invalid signature */
94 	HAB_INV_SIZE = 0x17,		/* Invalid data size */
95 	HAB_MEM_FAIL = 0x2e,		/* Memory failure */
96 	HAB_OVR_COUNT = 0x2b,		/* Expired poll count */
97 	HAB_OVR_STORAGE = 0x2d,		/* Exhausted storage region */
98 	HAB_UNS_ALGORITHM = 0x12,   /* Unsupported algorithm */
99 	HAB_UNS_COMMAND = 0x03,		/* Unsupported command */
100 	HAB_UNS_ENGINE = 0x0a,		/* Unsupported engine */
101 	HAB_UNS_ITEM = 0x24,		/* Unsupported configuration item */
102 	HAB_UNS_KEY = 0x1b,	        /* Unsupported key type/parameters */
103 	HAB_UNS_PROTOCOL = 0x14,	/* Unsupported protocol */
104 	HAB_UNS_STATE = 0x09,		/* Unsuitable state */
105 	HAB_RSN_MAX
106 };
107 
108 enum hab_context {
109 	HAB_CTX_ANY = 0x00,			/* Match any context */
110 	HAB_CTX_FAB = 0xff,		    /* Event logged in hab_fab_test() */
111 	HAB_CTX_ENTRY = 0xe1,		/* Event logged in hab_rvt.entry() */
112 	HAB_CTX_TARGET = 0x33,	    /* Event logged in hab_rvt.check_target() */
113 	HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
114 	HAB_CTX_DCD = 0xdd,         /* Event logged in hab_rvt.run_dcd() */
115 	HAB_CTX_CSF = 0xcf,         /* Event logged in hab_rvt.run_csf() */
116 	HAB_CTX_COMMAND = 0xc0,     /* Event logged executing csf/dcd command */
117 	HAB_CTX_AUT_DAT = 0xdb,		/* Authenticated data block */
118 	HAB_CTX_ASSERT = 0xa0,		/* Event logged in hab_rvt.assert() */
119 	HAB_CTX_EXIT = 0xee,		/* Event logged in hab_rvt.exit() */
120 	HAB_CTX_MAX
121 };
122 
123 enum hab_target {
124 	HAB_TGT_MEMORY		= 0x0f,
125 	HAB_TGT_PERIPHERAL	= 0xf0,
126 	HAB_TGT_ANY		= 0x55,
127 };
128 
129 struct imx_sec_config_fuse_t {
130 	int bank;
131 	int word;
132 };
133 
134 #if defined(CONFIG_SECURE_BOOT)
135 extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
136 #endif
137 
138 /*Function prototype description*/
139 typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
140 		uint8_t* , size_t*);
141 typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
142 		enum hab_state *);
143 typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
144 typedef enum hab_status hab_rvt_entry_t(void);
145 typedef enum hab_status hab_rvt_exit_t(void);
146 typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
147 		void **, size_t *, hab_loader_callback_f_t);
148 typedef enum hab_status hab_rvt_check_target_t(enum hab_target, const void *,
149 					       size_t);
150 typedef void hab_rvt_failsafe_t(void);
151 typedef void hapi_clock_init_t(void);
152 
153 #define HAB_ENG_ANY		0x00   /* Select first compatible engine */
154 #define HAB_ENG_SCC		0x03   /* Security controller */
155 #define HAB_ENG_RTIC	0x05   /* Run-time integrity checker */
156 #define HAB_ENG_SAHARA  0x06   /* Crypto accelerator */
157 #define HAB_ENG_CSU		0x0a   /* Central Security Unit */
158 #define HAB_ENG_SRTC	0x0c   /* Secure clock */
159 #define HAB_ENG_DCP		0x1b   /* Data Co-Processor */
160 #define HAB_ENG_CAAM	0x1d   /* CAAM */
161 #define HAB_ENG_SNVS	0x1e   /* Secure Non-Volatile Storage */
162 #define HAB_ENG_OCOTP	0x21   /* Fuse controller */
163 #define HAB_ENG_DTCP	0x22   /* DTCP co-processor */
164 #define HAB_ENG_ROM		0x36   /* Protected ROM area */
165 #define HAB_ENG_HDCP	0x24   /* HDCP co-processor */
166 #define HAB_ENG_RTL		0x77   /* RTL simulation engine */
167 #define HAB_ENG_SW		0xff   /* Software engine */
168 
169 #ifdef CONFIG_ROM_UNIFIED_SECTIONS
170 #define HAB_RVT_BASE			0x00000100
171 #else
172 #define HAB_RVT_BASE_NEW		0x00000098
173 #define HAB_RVT_BASE_OLD		0x00000094
174 #define HAB_RVT_BASE ((is_mx6dqp()) ?					\
175 			HAB_RVT_BASE_NEW :				\
176 			(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?	\
177 			HAB_RVT_BASE_NEW :				\
178 			(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?	\
179 			HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD)
180 #endif
181 
182 #define HAB_RVT_ENTRY			(*(uint32_t *)(HAB_RVT_BASE + 0x04))
183 #define HAB_RVT_EXIT			(*(uint32_t *)(HAB_RVT_BASE + 0x08))
184 #define HAB_RVT_CHECK_TARGET		(*(uint32_t *)(HAB_RVT_BASE + 0x0C))
185 #define HAB_RVT_AUTHENTICATE_IMAGE	(*(uint32_t *)(HAB_RVT_BASE + 0x10))
186 #define HAB_RVT_REPORT_EVENT		(*(uint32_t *)(HAB_RVT_BASE + 0x20))
187 #define HAB_RVT_REPORT_STATUS		(*(uint32_t *)(HAB_RVT_BASE + 0x24))
188 #define HAB_RVT_FAILSAFE		(*(uint32_t *)(HAB_RVT_BASE + 0x28))
189 
190 #define HAB_CID_ROM 0 /**< ROM Caller ID */
191 #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
192 
193 #define HAB_CMD_HDR          0xD4  /* CSF Header */
194 #define HAB_CMD_WRT_DAT      0xCC  /* Write Data command tag */
195 #define HAB_CMD_CHK_DAT      0xCF  /* Check Data command tag */
196 #define HAB_CMD_SET          0xB1  /* Set command tag */
197 #define HAB_PAR_MID          0x01  /* MID parameter value */
198 
199 #define IVT_SIZE			0x20
200 #define CSF_PAD_SIZE			0x2000
201 
202 /* ----------- end of HAB API updates ------------*/
203 
204 int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
205 			       uint32_t ivt_offset);
206 bool imx_hab_is_enabled(void);
207 
208 #endif
209