1 /* 2 * linux/include/asm-arm/io.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Modifications: 11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both 12 * constant addresses and variable addresses. 13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture 14 * specific IO header files. 15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. 16 * 04-Apr-1999 PJB Added check_signature. 17 * 12-Dec-1999 RMK More cleanups 18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions 19 */ 20 #ifndef __ASM_ARM_IO_H 21 #define __ASM_ARM_IO_H 22 23 #ifdef __KERNEL__ 24 25 #include <linux/types.h> 26 #include <asm/byteorder.h> 27 #include <asm/memory.h> 28 #if 0 /* XXX###XXX */ 29 #include <asm/arch/hardware.h> 30 #endif /* XXX###XXX */ 31 32 static inline void sync(void) 33 { 34 } 35 36 /* 37 * Given a physical address and a length, return a virtual address 38 * that can be used to access the memory range with the caching 39 * properties specified by "flags". 40 */ 41 #define MAP_NOCACHE (0) 42 #define MAP_WRCOMBINE (0) 43 #define MAP_WRBACK (0) 44 #define MAP_WRTHROUGH (0) 45 46 static inline void * 47 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) 48 { 49 return (void *)paddr; 50 } 51 52 /* 53 * Take down a mapping set up by map_physmem(). 54 */ 55 static inline void unmap_physmem(void *vaddr, unsigned long flags) 56 { 57 58 } 59 60 static inline phys_addr_t virt_to_phys(void * vaddr) 61 { 62 return (phys_addr_t)(vaddr); 63 } 64 65 /* 66 * Generic virtual read/write. Note that we don't support half-word 67 * read/writes. We define __arch_*[bl] here, and leave __arch_*w 68 * to the architecture specific code. 69 */ 70 #define __arch_getb(a) (*(volatile unsigned char *)(a)) 71 #define __arch_getw(a) (*(volatile unsigned short *)(a)) 72 #define __arch_getl(a) (*(volatile unsigned int *)(a)) 73 74 #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) 75 #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) 76 #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) 77 78 extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) 79 { 80 uint8_t *buf = (uint8_t *)data; 81 while(bytelen--) 82 __arch_putb(*buf++, addr); 83 } 84 85 extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) 86 { 87 uint16_t *buf = (uint16_t *)data; 88 while(wordlen--) 89 __arch_putw(*buf++, addr); 90 } 91 92 extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) 93 { 94 uint32_t *buf = (uint32_t *)data; 95 while(longlen--) 96 __arch_putl(*buf++, addr); 97 } 98 99 extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) 100 { 101 uint8_t *buf = (uint8_t *)data; 102 while(bytelen--) 103 *buf++ = __arch_getb(addr); 104 } 105 106 extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) 107 { 108 uint16_t *buf = (uint16_t *)data; 109 while(wordlen--) 110 *buf++ = __arch_getw(addr); 111 } 112 113 extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) 114 { 115 uint32_t *buf = (uint32_t *)data; 116 while(longlen--) 117 *buf++ = __arch_getl(addr); 118 } 119 120 #define __raw_writeb(v,a) __arch_putb(v,a) 121 #define __raw_writew(v,a) __arch_putw(v,a) 122 #define __raw_writel(v,a) __arch_putl(v,a) 123 124 #define __raw_readb(a) __arch_getb(a) 125 #define __raw_readw(a) __arch_getw(a) 126 #define __raw_readl(a) __arch_getl(a) 127 128 /* 129 * TODO: The kernel offers some more advanced versions of barriers, it might 130 * have some advantages to use them instead of the simple one here. 131 */ 132 #define dmb() __asm__ __volatile__ ("" : : : "memory") 133 #define __iormb() dmb() 134 #define __iowmb() dmb() 135 136 #define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) 137 #define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) 138 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) 139 140 #define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) 141 #define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) 142 #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) 143 144 /* 145 * The compiler seems to be incapable of optimising constants 146 * properly. Spell it out to the compiler in some cases. 147 * These are only valid for small values of "off" (< 1<<12) 148 */ 149 #define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) 150 #define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) 151 #define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) 152 153 #define __raw_base_readb(base,off) __arch_base_getb(base,off) 154 #define __raw_base_readw(base,off) __arch_base_getw(base,off) 155 #define __raw_base_readl(base,off) __arch_base_getl(base,off) 156 157 /* 158 * Clear and set bits in one shot. These macros can be used to clear and 159 * set multiple bits in a register using a single call. These macros can 160 * also be used to set a multiple-bit bit pattern using a mask, by 161 * specifying the mask in the 'clear' parameter and the new bit pattern 162 * in the 'set' parameter. 163 */ 164 165 #define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) 166 #define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) 167 168 #define out_le32(a,v) out_arch(l,le32,a,v) 169 #define out_le16(a,v) out_arch(w,le16,a,v) 170 171 #define in_le32(a) in_arch(l,le32,a) 172 #define in_le16(a) in_arch(w,le16,a) 173 174 #define out_be32(a,v) out_arch(l,be32,a,v) 175 #define out_be16(a,v) out_arch(w,be16,a,v) 176 177 #define in_be32(a) in_arch(l,be32,a) 178 #define in_be16(a) in_arch(w,be16,a) 179 180 #define out_8(a,v) __raw_writeb(v,a) 181 #define in_8(a) __raw_readb(a) 182 183 #define clrbits(type, addr, clear) \ 184 out_##type((addr), in_##type(addr) & ~(clear)) 185 186 #define setbits(type, addr, set) \ 187 out_##type((addr), in_##type(addr) | (set)) 188 189 #define clrsetbits(type, addr, clear, set) \ 190 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 191 192 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear) 193 #define setbits_be32(addr, set) setbits(be32, addr, set) 194 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 195 196 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear) 197 #define setbits_le32(addr, set) setbits(le32, addr, set) 198 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 199 200 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear) 201 #define setbits_be16(addr, set) setbits(be16, addr, set) 202 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 203 204 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear) 205 #define setbits_le16(addr, set) setbits(le16, addr, set) 206 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 207 208 #define clrbits_8(addr, clear) clrbits(8, addr, clear) 209 #define setbits_8(addr, set) setbits(8, addr, set) 210 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 211 212 /* 213 * Now, pick up the machine-defined IO definitions 214 */ 215 #if 0 /* XXX###XXX */ 216 #include <asm/arch/io.h> 217 #endif /* XXX###XXX */ 218 219 /* 220 * IO port access primitives 221 * ------------------------- 222 * 223 * The ARM doesn't have special IO access instructions; all IO is memory 224 * mapped. Note that these are defined to perform little endian accesses 225 * only. Their primary purpose is to access PCI and ISA peripherals. 226 * 227 * Note that for a big endian machine, this implies that the following 228 * big endian mode connectivity is in place, as described by numerous 229 * ARM documents: 230 * 231 * PCI: D0-D7 D8-D15 D16-D23 D24-D31 232 * ARM: D24-D31 D16-D23 D8-D15 D0-D7 233 * 234 * The machine specific io.h include defines __io to translate an "IO" 235 * address to a memory address. 236 * 237 * Note that we prevent GCC re-ordering or caching values in expressions 238 * by introducing sequence points into the in*() definitions. Note that 239 * __raw_* do not guarantee this behaviour. 240 * 241 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. 242 */ 243 #ifdef __io 244 #define outb(v,p) __raw_writeb(v,__io(p)) 245 #define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) 246 #define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) 247 248 #define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) 249 #define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) 250 #define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) 251 252 #define outsb(p,d,l) __raw_writesb(__io(p),d,l) 253 #define outsw(p,d,l) __raw_writesw(__io(p),d,l) 254 #define outsl(p,d,l) __raw_writesl(__io(p),d,l) 255 256 #define insb(p,d,l) __raw_readsb(__io(p),d,l) 257 #define insw(p,d,l) __raw_readsw(__io(p),d,l) 258 #define insl(p,d,l) __raw_readsl(__io(p),d,l) 259 #endif 260 261 #define outb_p(val,port) outb((val),(port)) 262 #define outw_p(val,port) outw((val),(port)) 263 #define outl_p(val,port) outl((val),(port)) 264 #define inb_p(port) inb((port)) 265 #define inw_p(port) inw((port)) 266 #define inl_p(port) inl((port)) 267 268 #define outsb_p(port,from,len) outsb(port,from,len) 269 #define outsw_p(port,from,len) outsw(port,from,len) 270 #define outsl_p(port,from,len) outsl(port,from,len) 271 #define insb_p(port,to,len) insb(port,to,len) 272 #define insw_p(port,to,len) insw(port,to,len) 273 #define insl_p(port,to,len) insl(port,to,len) 274 275 /* 276 * ioremap and friends. 277 * 278 * ioremap takes a PCI memory address, as specified in 279 * linux/Documentation/IO-mapping.txt. If you want a 280 * physical address, use __ioremap instead. 281 */ 282 extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); 283 extern void __iounmap(void *addr); 284 285 /* 286 * Generic ioremap support. 287 * 288 * Define: 289 * iomem_valid_addr(off,size) 290 * iomem_to_phys(off) 291 */ 292 #ifdef iomem_valid_addr 293 #define __arch_ioremap(off,sz,nocache) \ 294 ({ \ 295 unsigned long _off = (off), _size = (sz); \ 296 void *_ret = (void *)0; \ 297 if (iomem_valid_addr(_off, _size)) \ 298 _ret = __ioremap(iomem_to_phys(_off),_size,nocache); \ 299 _ret; \ 300 }) 301 302 #define __arch_iounmap __iounmap 303 #endif 304 305 #define ioremap(off,sz) __arch_ioremap((off),(sz),0) 306 #define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) 307 #define iounmap(_addr) __arch_iounmap(_addr) 308 309 /* 310 * DMA-consistent mapping functions. These allocate/free a region of 311 * uncached, unwrite-buffered mapped memory space for use with DMA 312 * devices. This is the "generic" version. The PCI specific version 313 * is in pci.h 314 */ 315 extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); 316 extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); 317 extern void consistent_sync(void *vaddr, size_t size, int rw); 318 319 /* 320 * String version of IO memory access ops: 321 */ 322 extern void _memcpy_fromio(void *, unsigned long, size_t); 323 extern void _memcpy_toio(unsigned long, const void *, size_t); 324 extern void _memset_io(unsigned long, int, size_t); 325 326 extern void __readwrite_bug(const char *fn); 327 328 /* 329 * If this architecture has PCI memory IO, then define the read/write 330 * macros. These should only be used with the cookie passed from 331 * ioremap. 332 */ 333 #ifdef __mem_pci 334 335 #define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) 336 #define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) 337 #define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) 338 339 #define writeb(v,c) __raw_writeb(v,__mem_pci(c)) 340 #define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) 341 #define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) 342 343 #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) 344 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) 345 #define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) 346 347 #define eth_io_copy_and_sum(s,c,l,b) \ 348 eth_copy_and_sum((s),__mem_pci(c),(l),(b)) 349 350 static inline int 351 check_signature(unsigned long io_addr, const unsigned char *signature, 352 int length) 353 { 354 int retval = 0; 355 do { 356 if (readb(io_addr) != *signature) 357 goto out; 358 io_addr++; 359 signature++; 360 length--; 361 } while (length); 362 retval = 1; 363 out: 364 return retval; 365 } 366 367 #elif !defined(readb) 368 369 #define readb(addr) (__readwrite_bug("readb"),0) 370 #define readw(addr) (__readwrite_bug("readw"),0) 371 #define readl(addr) (__readwrite_bug("readl"),0) 372 #define writeb(v,addr) __readwrite_bug("writeb") 373 #define writew(v,addr) __readwrite_bug("writew") 374 #define writel(v,addr) __readwrite_bug("writel") 375 376 #define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") 377 378 #define check_signature(io,sig,len) (0) 379 380 #endif /* __mem_pci */ 381 382 /* 383 * If this architecture has ISA IO, then define the isa_read/isa_write 384 * macros. 385 */ 386 #ifdef __mem_isa 387 388 #define isa_readb(addr) __raw_readb(__mem_isa(addr)) 389 #define isa_readw(addr) __raw_readw(__mem_isa(addr)) 390 #define isa_readl(addr) __raw_readl(__mem_isa(addr)) 391 #define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) 392 #define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) 393 #define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) 394 #define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) 395 #define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) 396 #define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) 397 398 #define isa_eth_io_copy_and_sum(a,b,c,d) \ 399 eth_copy_and_sum((a),__mem_isa(b),(c),(d)) 400 401 static inline int 402 isa_check_signature(unsigned long io_addr, const unsigned char *signature, 403 int length) 404 { 405 int retval = 0; 406 do { 407 if (isa_readb(io_addr) != *signature) 408 goto out; 409 io_addr++; 410 signature++; 411 length--; 412 } while (length); 413 retval = 1; 414 out: 415 return retval; 416 } 417 418 #else /* __mem_isa */ 419 420 #define isa_readb(addr) (__readwrite_bug("isa_readb"),0) 421 #define isa_readw(addr) (__readwrite_bug("isa_readw"),0) 422 #define isa_readl(addr) (__readwrite_bug("isa_readl"),0) 423 #define isa_writeb(val,addr) __readwrite_bug("isa_writeb") 424 #define isa_writew(val,addr) __readwrite_bug("isa_writew") 425 #define isa_writel(val,addr) __readwrite_bug("isa_writel") 426 #define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") 427 #define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") 428 #define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") 429 430 #define isa_eth_io_copy_and_sum(a,b,c,d) \ 431 __readwrite_bug("isa_eth_io_copy_and_sum") 432 433 #define isa_check_signature(io,sig,len) (0) 434 435 #endif /* __mem_isa */ 436 #endif /* __KERNEL__ */ 437 #endif /* __ASM_ARM_IO_H */ 438