1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_SECURE_BOOT_H 8 #define __FSL_SECURE_BOOT_H 9 10 #ifdef CONFIG_SECURE_BOOT 11 12 #ifndef CONFIG_FIT_SIGNATURE 13 #define CONFIG_CHAIN_OF_TRUST 14 #endif 15 16 #endif 17 18 #ifdef CONFIG_CHAIN_OF_TRUST 19 #define CONFIG_CMD_ESBC_VALIDATE 20 #define CONFIG_FSL_SEC_MON 21 #define CONFIG_SHA_HW_ACCEL 22 #define CONFIG_SHA_PROG_HW_ACCEL 23 #define CONFIG_RSA_FREESCALE_EXP 24 25 #ifndef CONFIG_FSL_CAAM 26 #define CONFIG_FSL_CAAM 27 #endif 28 29 #define CONFIG_SPL_BOARD_INIT 30 #ifdef CONFIG_SPL_BUILD 31 /* 32 * Define the key hash for U-Boot here if public/private key pair used to 33 * sign U-boot are different from the SRK hash put in the fuse 34 * Example of defining KEY_HASH is 35 * #define CONFIG_SPL_UBOOT_KEY_HASH \ 36 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 37 * else leave it defined as NULL 38 */ 39 40 #define CONFIG_SPL_UBOOT_KEY_HASH NULL 41 #endif /* ifdef CONFIG_SPL_BUILD */ 42 43 #ifndef CONFIG_SPL_BUILD 44 #define CONFIG_CMD_BLOB 45 #define CONFIG_CMD_HASH 46 #define CONFIG_KEY_REVOCATION 47 #ifndef CONFIG_SYS_RAMBOOT 48 /* The key used for verification of next level images 49 * is picked up from an Extension Table which has 50 * been verified by the ISBC (Internal Secure boot Code) 51 * in boot ROM of the SoC. 52 * The feature is only applicable in case of NOR boot and is 53 * not applicable in case of RAMBOOT (NAND, SD, SPI). 54 */ 55 #ifndef CONFIG_ESBC_HDR_LS 56 /* Current Key EXT feature not available in LS ESBC Header */ 57 #define CONFIG_FSL_ISBC_KEY_EXT 58 #endif 59 60 #endif 61 62 #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) 63 /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit 64 * Similiarly for LS2080 65 */ 66 #define CONFIG_ESBC_ADDR_64BIT 67 #endif 68 69 #ifdef CONFIG_LS2080A 70 #define CONFIG_EXTRA_ENV \ 71 "setenv fdt_high 0xa0000000;" \ 72 "setenv initrd_high 0xcfffffff;" \ 73 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 74 #else 75 #define CONFIG_EXTRA_ENV \ 76 "setenv fdt_high 0xffffffff;" \ 77 "setenv initrd_high 0xffffffff;" \ 78 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 79 #endif 80 81 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from 82 * Non-XIP Memory (Nand/SD)*/ 83 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ 84 defined(CONFIG_SD_BOOT) 85 #define CONFIG_BOOTSCRIPT_COPY_RAM 86 #endif 87 /* The address needs to be modified according to NOR, NAND, SD and 88 * DDR memory map 89 */ 90 #ifdef CONFIG_LS2080A 91 #define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 92 #define CONFIG_BS_ADDR_DEVICE 0x583900000 93 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 94 #define CONFIG_BS_ADDR_RAM 0xa3900000 95 #define CONFIG_BS_HDR_SIZE 0x00002000 96 #define CONFIG_BS_SIZE 0x00001000 97 #else 98 #ifdef CONFIG_SD_BOOT 99 /* For SD boot address and size are assigned in terms of sector 100 * offset and no. of sectors respectively. 101 */ 102 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800 103 #define CONFIG_BS_ADDR_DEVICE 0x00000840 104 #define CONFIG_BS_HDR_SIZE 0x00000010 105 #define CONFIG_BS_SIZE 0x00000008 106 #else 107 #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 108 #define CONFIG_BS_ADDR_DEVICE 0x60060000 109 #define CONFIG_BS_HDR_SIZE 0x00002000 110 #define CONFIG_BS_SIZE 0x00001000 111 #endif /* #ifdef CONFIG_SD_BOOT */ 112 #define CONFIG_BS_HDR_ADDR_RAM 0x81000000 113 #define CONFIG_BS_ADDR_RAM 0x81020000 114 #endif 115 116 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 117 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 118 #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM 119 #else 120 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE 121 /* BOOTSCRIPT_ADDR is not required */ 122 #endif 123 124 #include <config_fsl_chain_trust.h> 125 #endif /* #ifndef CONFIG_SPL_BUILD */ 126 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 127 #endif 128