xref: /openbmc/u-boot/arch/arm/include/asm/emif.h (revision dfe6f4d6)
1 /*
2  * OMAP44xx EMIF header
3  *
4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
5  *
6  * Aneesh V <aneesh@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #ifndef _EMIF_H_
14 #define _EMIF_H_
15 #include <asm/types.h>
16 #include <common.h>
17 #include <asm/io.h>
18 
19 /* Base address */
20 #define EMIF1_BASE				0x4c000000
21 #define EMIF2_BASE				0x4d000000
22 
23 #define EMIF_4D					0x4
24 #define EMIF_4D5				0x5
25 
26 /* Registers shifts, masks and values */
27 
28 /* EMIF_MOD_ID_REV */
29 #define EMIF_REG_SCHEME_SHIFT			30
30 #define EMIF_REG_SCHEME_MASK			(0x3 << 30)
31 #define EMIF_REG_MODULE_ID_SHIFT			16
32 #define EMIF_REG_MODULE_ID_MASK			(0xfff << 16)
33 #define EMIF_REG_RTL_VERSION_SHIFT			11
34 #define EMIF_REG_RTL_VERSION_MASK			(0x1f << 11)
35 #define EMIF_REG_MAJOR_REVISION_SHIFT		8
36 #define EMIF_REG_MAJOR_REVISION_MASK		(0x7 << 8)
37 #define EMIF_REG_MINOR_REVISION_SHIFT		0
38 #define EMIF_REG_MINOR_REVISION_MASK		(0x3f << 0)
39 
40 /* STATUS */
41 #define EMIF_REG_BE_SHIFT				31
42 #define EMIF_REG_BE_MASK				(1 << 31)
43 #define EMIF_REG_DUAL_CLK_MODE_SHIFT		30
44 #define EMIF_REG_DUAL_CLK_MODE_MASK			(1 << 30)
45 #define EMIF_REG_FAST_INIT_SHIFT			29
46 #define EMIF_REG_FAST_INIT_MASK			(1 << 29)
47 #define EMIF_REG_PHY_DLL_READY_SHIFT		2
48 #define EMIF_REG_PHY_DLL_READY_MASK			(1 << 2)
49 
50 /* SDRAM_CONFIG */
51 #define EMIF_REG_SDRAM_TYPE_SHIFT			29
52 #define EMIF_REG_SDRAM_TYPE_MASK			(0x7 << 29)
53 #define EMIF_REG_SDRAM_TYPE_DDR1			0
54 #define EMIF_REG_SDRAM_TYPE_LPDDR1			1
55 #define EMIF_REG_SDRAM_TYPE_DDR2			2
56 #define EMIF_REG_SDRAM_TYPE_DDR3			3
57 #define EMIF_REG_SDRAM_TYPE_LPDDR2_S4			4
58 #define EMIF_REG_SDRAM_TYPE_LPDDR2_S2			5
59 #define EMIF_REG_IBANK_POS_SHIFT			27
60 #define EMIF_REG_IBANK_POS_MASK			(0x3 << 27)
61 #define EMIF_REG_DDR_TERM_SHIFT			24
62 #define EMIF_REG_DDR_TERM_MASK			(0x7 << 24)
63 #define EMIF_REG_DDR2_DDQS_SHIFT			23
64 #define EMIF_REG_DDR2_DDQS_MASK			(1 << 23)
65 #define EMIF_REG_DYN_ODT_SHIFT			21
66 #define EMIF_REG_DYN_ODT_MASK			(0x3 << 21)
67 #define EMIF_REG_DDR_DISABLE_DLL_SHIFT		20
68 #define EMIF_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
69 #define EMIF_REG_SDRAM_DRIVE_SHIFT			18
70 #define EMIF_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
71 #define EMIF_REG_CWL_SHIFT				16
72 #define EMIF_REG_CWL_MASK				(0x3 << 16)
73 #define EMIF_REG_NARROW_MODE_SHIFT			14
74 #define EMIF_REG_NARROW_MODE_MASK			(0x3 << 14)
75 #define EMIF_REG_CL_SHIFT				10
76 #define EMIF_REG_CL_MASK				(0xf << 10)
77 #define EMIF_REG_ROWSIZE_SHIFT			7
78 #define EMIF_REG_ROWSIZE_MASK			(0x7 << 7)
79 #define EMIF_REG_IBANK_SHIFT			4
80 #define EMIF_REG_IBANK_MASK				(0x7 << 4)
81 #define EMIF_REG_EBANK_SHIFT			3
82 #define EMIF_REG_EBANK_MASK				(1 << 3)
83 #define EMIF_REG_PAGESIZE_SHIFT			0
84 #define EMIF_REG_PAGESIZE_MASK			(0x7 << 0)
85 
86 /* SDRAM_CONFIG_2 */
87 #define EMIF_REG_CS1NVMEN_SHIFT			30
88 #define EMIF_REG_CS1NVMEN_MASK			(1 << 30)
89 #define EMIF_REG_EBANK_POS_SHIFT			27
90 #define EMIF_REG_EBANK_POS_MASK			(1 << 27)
91 #define EMIF_REG_RDBNUM_SHIFT			4
92 #define EMIF_REG_RDBNUM_MASK			(0x3 << 4)
93 #define EMIF_REG_RDBSIZE_SHIFT			0
94 #define EMIF_REG_RDBSIZE_MASK			(0x7 << 0)
95 
96 /* SDRAM_REF_CTRL */
97 #define EMIF_REG_INITREF_DIS_SHIFT			31
98 #define EMIF_REG_INITREF_DIS_MASK			(1 << 31)
99 #define EMIF_REG_SRT_SHIFT				29
100 #define EMIF_REG_SRT_MASK				(1 << 29)
101 #define EMIF_REG_ASR_SHIFT				28
102 #define EMIF_REG_ASR_MASK				(1 << 28)
103 #define EMIF_REG_PASR_SHIFT				24
104 #define EMIF_REG_PASR_MASK				(0x7 << 24)
105 #define EMIF_REG_REFRESH_RATE_SHIFT			0
106 #define EMIF_REG_REFRESH_RATE_MASK			(0xffff << 0)
107 
108 /* SDRAM_REF_CTRL_SHDW */
109 #define EMIF_REG_REFRESH_RATE_SHDW_SHIFT		0
110 #define EMIF_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
111 
112 /* SDRAM_TIM_1 */
113 #define EMIF_REG_T_RP_SHIFT				25
114 #define EMIF_REG_T_RP_MASK				(0xf << 25)
115 #define EMIF_REG_T_RCD_SHIFT			21
116 #define EMIF_REG_T_RCD_MASK				(0xf << 21)
117 #define EMIF_REG_T_WR_SHIFT				17
118 #define EMIF_REG_T_WR_MASK				(0xf << 17)
119 #define EMIF_REG_T_RAS_SHIFT			12
120 #define EMIF_REG_T_RAS_MASK				(0x1f << 12)
121 #define EMIF_REG_T_RC_SHIFT				6
122 #define EMIF_REG_T_RC_MASK				(0x3f << 6)
123 #define EMIF_REG_T_RRD_SHIFT			3
124 #define EMIF_REG_T_RRD_MASK				(0x7 << 3)
125 #define EMIF_REG_T_WTR_SHIFT			0
126 #define EMIF_REG_T_WTR_MASK				(0x7 << 0)
127 
128 /* SDRAM_TIM_1_SHDW */
129 #define EMIF_REG_T_RP_SHDW_SHIFT			25
130 #define EMIF_REG_T_RP_SHDW_MASK			(0xf << 25)
131 #define EMIF_REG_T_RCD_SHDW_SHIFT			21
132 #define EMIF_REG_T_RCD_SHDW_MASK			(0xf << 21)
133 #define EMIF_REG_T_WR_SHDW_SHIFT			17
134 #define EMIF_REG_T_WR_SHDW_MASK			(0xf << 17)
135 #define EMIF_REG_T_RAS_SHDW_SHIFT			12
136 #define EMIF_REG_T_RAS_SHDW_MASK			(0x1f << 12)
137 #define EMIF_REG_T_RC_SHDW_SHIFT			6
138 #define EMIF_REG_T_RC_SHDW_MASK			(0x3f << 6)
139 #define EMIF_REG_T_RRD_SHDW_SHIFT			3
140 #define EMIF_REG_T_RRD_SHDW_MASK			(0x7 << 3)
141 #define EMIF_REG_T_WTR_SHDW_SHIFT			0
142 #define EMIF_REG_T_WTR_SHDW_MASK			(0x7 << 0)
143 
144 /* SDRAM_TIM_2 */
145 #define EMIF_REG_T_XP_SHIFT				28
146 #define EMIF_REG_T_XP_MASK				(0x7 << 28)
147 #define EMIF_REG_T_ODT_SHIFT			25
148 #define EMIF_REG_T_ODT_MASK				(0x7 << 25)
149 #define EMIF_REG_T_XSNR_SHIFT			16
150 #define EMIF_REG_T_XSNR_MASK			(0x1ff << 16)
151 #define EMIF_REG_T_XSRD_SHIFT			6
152 #define EMIF_REG_T_XSRD_MASK			(0x3ff << 6)
153 #define EMIF_REG_T_RTP_SHIFT			3
154 #define EMIF_REG_T_RTP_MASK				(0x7 << 3)
155 #define EMIF_REG_T_CKE_SHIFT			0
156 #define EMIF_REG_T_CKE_MASK				(0x7 << 0)
157 
158 /* SDRAM_TIM_2_SHDW */
159 #define EMIF_REG_T_XP_SHDW_SHIFT			28
160 #define EMIF_REG_T_XP_SHDW_MASK			(0x7 << 28)
161 #define EMIF_REG_T_ODT_SHDW_SHIFT			25
162 #define EMIF_REG_T_ODT_SHDW_MASK			(0x7 << 25)
163 #define EMIF_REG_T_XSNR_SHDW_SHIFT			16
164 #define EMIF_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
165 #define EMIF_REG_T_XSRD_SHDW_SHIFT			6
166 #define EMIF_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
167 #define EMIF_REG_T_RTP_SHDW_SHIFT			3
168 #define EMIF_REG_T_RTP_SHDW_MASK			(0x7 << 3)
169 #define EMIF_REG_T_CKE_SHDW_SHIFT			0
170 #define EMIF_REG_T_CKE_SHDW_MASK			(0x7 << 0)
171 
172 /* SDRAM_TIM_3 */
173 #define EMIF_REG_T_CKESR_SHIFT			21
174 #define EMIF_REG_T_CKESR_MASK			(0x7 << 21)
175 #define EMIF_REG_ZQ_ZQCS_SHIFT			15
176 #define EMIF_REG_ZQ_ZQCS_MASK			(0x3f << 15)
177 #define EMIF_REG_T_TDQSCKMAX_SHIFT			13
178 #define EMIF_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
179 #define EMIF_REG_T_RFC_SHIFT			4
180 #define EMIF_REG_T_RFC_MASK				(0x1ff << 4)
181 #define EMIF_REG_T_RAS_MAX_SHIFT			0
182 #define EMIF_REG_T_RAS_MAX_MASK			(0xf << 0)
183 
184 /* SDRAM_TIM_3_SHDW */
185 #define EMIF_REG_T_CKESR_SHDW_SHIFT			21
186 #define EMIF_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
187 #define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT			15
188 #define EMIF_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
189 #define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT		13
190 #define EMIF_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
191 #define EMIF_REG_T_RFC_SHDW_SHIFT			4
192 #define EMIF_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
193 #define EMIF_REG_T_RAS_MAX_SHDW_SHIFT		0
194 #define EMIF_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
195 
196 /* LPDDR2_NVM_TIM */
197 #define EMIF_REG_NVM_T_XP_SHIFT			28
198 #define EMIF_REG_NVM_T_XP_MASK			(0x7 << 28)
199 #define EMIF_REG_NVM_T_WTR_SHIFT			24
200 #define EMIF_REG_NVM_T_WTR_MASK			(0x7 << 24)
201 #define EMIF_REG_NVM_T_RP_SHIFT			20
202 #define EMIF_REG_NVM_T_RP_MASK			(0xf << 20)
203 #define EMIF_REG_NVM_T_WRA_SHIFT			16
204 #define EMIF_REG_NVM_T_WRA_MASK			(0xf << 16)
205 #define EMIF_REG_NVM_T_RRD_SHIFT			8
206 #define EMIF_REG_NVM_T_RRD_MASK			(0xff << 8)
207 #define EMIF_REG_NVM_T_RCDMIN_SHIFT			0
208 #define EMIF_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
209 
210 /* LPDDR2_NVM_TIM_SHDW */
211 #define EMIF_REG_NVM_T_XP_SHDW_SHIFT		28
212 #define EMIF_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
213 #define EMIF_REG_NVM_T_WTR_SHDW_SHIFT		24
214 #define EMIF_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
215 #define EMIF_REG_NVM_T_RP_SHDW_SHIFT		20
216 #define EMIF_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
217 #define EMIF_REG_NVM_T_WRA_SHDW_SHIFT		16
218 #define EMIF_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
219 #define EMIF_REG_NVM_T_RRD_SHDW_SHIFT		8
220 #define EMIF_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
221 #define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
222 #define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
223 
224 /* PWR_MGMT_CTRL */
225 #define EMIF_REG_IDLEMODE_SHIFT			30
226 #define EMIF_REG_IDLEMODE_MASK			(0x3 << 30)
227 #define EMIF_REG_PD_TIM_SHIFT			12
228 #define EMIF_REG_PD_TIM_MASK			(0xf << 12)
229 #define EMIF_REG_DPD_EN_SHIFT			11
230 #define EMIF_REG_DPD_EN_MASK			(1 << 11)
231 #define EMIF_REG_LP_MODE_SHIFT			8
232 #define EMIF_REG_LP_MODE_MASK			(0x7 << 8)
233 #define EMIF_REG_SR_TIM_SHIFT			4
234 #define EMIF_REG_SR_TIM_MASK			(0xf << 4)
235 #define EMIF_REG_CS_TIM_SHIFT			0
236 #define EMIF_REG_CS_TIM_MASK			(0xf << 0)
237 
238 /* PWR_MGMT_CTRL_SHDW */
239 #define EMIF_REG_PD_TIM_SHDW_SHIFT			12
240 #define EMIF_REG_PD_TIM_SHDW_MASK			(0xf << 12)
241 #define EMIF_REG_SR_TIM_SHDW_SHIFT			4
242 #define EMIF_REG_SR_TIM_SHDW_MASK			(0xf << 4)
243 #define EMIF_REG_CS_TIM_SHDW_SHIFT			0
244 #define EMIF_REG_CS_TIM_SHDW_MASK			(0xf << 0)
245 
246 /* LPDDR2_MODE_REG_DATA */
247 #define EMIF_REG_VALUE_0_SHIFT			0
248 #define EMIF_REG_VALUE_0_MASK			(0x7f << 0)
249 
250 /* LPDDR2_MODE_REG_CFG */
251 #define EMIF_REG_CS_SHIFT				31
252 #define EMIF_REG_CS_MASK				(1 << 31)
253 #define EMIF_REG_REFRESH_EN_SHIFT			30
254 #define EMIF_REG_REFRESH_EN_MASK			(1 << 30)
255 #define EMIF_REG_ADDRESS_SHIFT			0
256 #define EMIF_REG_ADDRESS_MASK			(0xff << 0)
257 
258 /* OCP_CONFIG */
259 #define EMIF_REG_SYS_THRESH_MAX_SHIFT		24
260 #define EMIF_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
261 #define EMIF_REG_MPU_THRESH_MAX_SHIFT		20
262 #define EMIF_REG_MPU_THRESH_MAX_MASK		(0xf << 20)
263 #define EMIF_REG_LL_THRESH_MAX_SHIFT		16
264 #define EMIF_REG_LL_THRESH_MAX_MASK			(0xf << 16)
265 #define EMIF_REG_PR_OLD_COUNT_SHIFT			0
266 #define EMIF_REG_PR_OLD_COUNT_MASK			(0xff << 0)
267 
268 /* OCP_CFG_VAL_1 */
269 #define EMIF_REG_SYS_BUS_WIDTH_SHIFT		30
270 #define EMIF_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
271 #define EMIF_REG_LL_BUS_WIDTH_SHIFT			28
272 #define EMIF_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
273 #define EMIF_REG_WR_FIFO_DEPTH_SHIFT		8
274 #define EMIF_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
275 #define EMIF_REG_CMD_FIFO_DEPTH_SHIFT		0
276 #define EMIF_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
277 
278 /* OCP_CFG_VAL_2 */
279 #define EMIF_REG_RREG_FIFO_DEPTH_SHIFT		16
280 #define EMIF_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
281 #define EMIF_REG_RSD_FIFO_DEPTH_SHIFT		8
282 #define EMIF_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
283 #define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT		0
284 #define EMIF_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
285 
286 /* IODFT_TLGC */
287 #define EMIF_REG_TLEC_SHIFT				16
288 #define EMIF_REG_TLEC_MASK				(0xffff << 16)
289 #define EMIF_REG_MT_SHIFT				14
290 #define EMIF_REG_MT_MASK				(1 << 14)
291 #define EMIF_REG_ACT_CAP_EN_SHIFT			13
292 #define EMIF_REG_ACT_CAP_EN_MASK			(1 << 13)
293 #define EMIF_REG_OPG_LD_SHIFT			12
294 #define EMIF_REG_OPG_LD_MASK			(1 << 12)
295 #define EMIF_REG_RESET_PHY_SHIFT			10
296 #define EMIF_REG_RESET_PHY_MASK			(1 << 10)
297 #define EMIF_REG_MMS_SHIFT				8
298 #define EMIF_REG_MMS_MASK				(1 << 8)
299 #define EMIF_REG_MC_SHIFT				4
300 #define EMIF_REG_MC_MASK				(0x3 << 4)
301 #define EMIF_REG_PC_SHIFT				1
302 #define EMIF_REG_PC_MASK				(0x7 << 1)
303 #define EMIF_REG_TM_SHIFT				0
304 #define EMIF_REG_TM_MASK				(1 << 0)
305 
306 /* IODFT_CTRL_MISR_RSLT */
307 #define EMIF_REG_DQM_TLMR_SHIFT			16
308 #define EMIF_REG_DQM_TLMR_MASK			(0x3ff << 16)
309 #define EMIF_REG_CTL_TLMR_SHIFT			0
310 #define EMIF_REG_CTL_TLMR_MASK			(0x7ff << 0)
311 
312 /* IODFT_ADDR_MISR_RSLT */
313 #define EMIF_REG_ADDR_TLMR_SHIFT			0
314 #define EMIF_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
315 
316 /* IODFT_DATA_MISR_RSLT_1 */
317 #define EMIF_REG_DATA_TLMR_31_0_SHIFT		0
318 #define EMIF_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
319 
320 /* IODFT_DATA_MISR_RSLT_2 */
321 #define EMIF_REG_DATA_TLMR_63_32_SHIFT		0
322 #define EMIF_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
323 
324 /* IODFT_DATA_MISR_RSLT_3 */
325 #define EMIF_REG_DATA_TLMR_66_64_SHIFT		0
326 #define EMIF_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
327 
328 /* PERF_CNT_1 */
329 #define EMIF_REG_COUNTER1_SHIFT			0
330 #define EMIF_REG_COUNTER1_MASK			(0xffffffff << 0)
331 
332 /* PERF_CNT_2 */
333 #define EMIF_REG_COUNTER2_SHIFT			0
334 #define EMIF_REG_COUNTER2_MASK			(0xffffffff << 0)
335 
336 /* PERF_CNT_CFG */
337 #define EMIF_REG_CNTR2_MCONNID_EN_SHIFT		31
338 #define EMIF_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
339 #define EMIF_REG_CNTR2_REGION_EN_SHIFT		30
340 #define EMIF_REG_CNTR2_REGION_EN_MASK		(1 << 30)
341 #define EMIF_REG_CNTR2_CFG_SHIFT			16
342 #define EMIF_REG_CNTR2_CFG_MASK			(0xf << 16)
343 #define EMIF_REG_CNTR1_MCONNID_EN_SHIFT		15
344 #define EMIF_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
345 #define EMIF_REG_CNTR1_REGION_EN_SHIFT		14
346 #define EMIF_REG_CNTR1_REGION_EN_MASK		(1 << 14)
347 #define EMIF_REG_CNTR1_CFG_SHIFT			0
348 #define EMIF_REG_CNTR1_CFG_MASK			(0xf << 0)
349 
350 /* PERF_CNT_SEL */
351 #define EMIF_REG_MCONNID2_SHIFT			24
352 #define EMIF_REG_MCONNID2_MASK			(0xff << 24)
353 #define EMIF_REG_REGION_SEL2_SHIFT			16
354 #define EMIF_REG_REGION_SEL2_MASK			(0x3 << 16)
355 #define EMIF_REG_MCONNID1_SHIFT			8
356 #define EMIF_REG_MCONNID1_MASK			(0xff << 8)
357 #define EMIF_REG_REGION_SEL1_SHIFT			0
358 #define EMIF_REG_REGION_SEL1_MASK			(0x3 << 0)
359 
360 /* PERF_CNT_TIM */
361 #define EMIF_REG_TOTAL_TIME_SHIFT			0
362 #define EMIF_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
363 
364 /* READ_IDLE_CTRL */
365 #define EMIF_REG_READ_IDLE_LEN_SHIFT		16
366 #define EMIF_REG_READ_IDLE_LEN_MASK			(0xf << 16)
367 #define EMIF_REG_READ_IDLE_INTERVAL_SHIFT		0
368 #define EMIF_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
369 
370 /* READ_IDLE_CTRL_SHDW */
371 #define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT		16
372 #define EMIF_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
373 #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
374 #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
375 
376 /* IRQ_EOI */
377 #define EMIF_REG_EOI_SHIFT				0
378 #define EMIF_REG_EOI_MASK				(1 << 0)
379 
380 /* IRQSTATUS_RAW_SYS */
381 #define EMIF_REG_DNV_SYS_SHIFT			2
382 #define EMIF_REG_DNV_SYS_MASK			(1 << 2)
383 #define EMIF_REG_TA_SYS_SHIFT			1
384 #define EMIF_REG_TA_SYS_MASK			(1 << 1)
385 #define EMIF_REG_ERR_SYS_SHIFT			0
386 #define EMIF_REG_ERR_SYS_MASK			(1 << 0)
387 
388 /* IRQSTATUS_RAW_LL */
389 #define EMIF_REG_DNV_LL_SHIFT			2
390 #define EMIF_REG_DNV_LL_MASK			(1 << 2)
391 #define EMIF_REG_TA_LL_SHIFT			1
392 #define EMIF_REG_TA_LL_MASK				(1 << 1)
393 #define EMIF_REG_ERR_LL_SHIFT			0
394 #define EMIF_REG_ERR_LL_MASK			(1 << 0)
395 
396 /* IRQSTATUS_SYS */
397 
398 /* IRQSTATUS_LL */
399 
400 /* IRQENABLE_SET_SYS */
401 #define EMIF_REG_EN_DNV_SYS_SHIFT			2
402 #define EMIF_REG_EN_DNV_SYS_MASK			(1 << 2)
403 #define EMIF_REG_EN_TA_SYS_SHIFT			1
404 #define EMIF_REG_EN_TA_SYS_MASK			(1 << 1)
405 #define EMIF_REG_EN_ERR_SYS_SHIFT			0
406 #define EMIF_REG_EN_ERR_SYS_MASK			(1 << 0)
407 
408 /* IRQENABLE_SET_LL */
409 #define EMIF_REG_EN_DNV_LL_SHIFT			2
410 #define EMIF_REG_EN_DNV_LL_MASK			(1 << 2)
411 #define EMIF_REG_EN_TA_LL_SHIFT			1
412 #define EMIF_REG_EN_TA_LL_MASK			(1 << 1)
413 #define EMIF_REG_EN_ERR_LL_SHIFT			0
414 #define EMIF_REG_EN_ERR_LL_MASK			(1 << 0)
415 
416 /* IRQENABLE_CLR_SYS */
417 
418 /* IRQENABLE_CLR_LL */
419 
420 /* ZQ_CONFIG */
421 #define EMIF_REG_ZQ_CS1EN_SHIFT			31
422 #define EMIF_REG_ZQ_CS1EN_MASK			(1 << 31)
423 #define EMIF_REG_ZQ_CS0EN_SHIFT			30
424 #define EMIF_REG_ZQ_CS0EN_MASK			(1 << 30)
425 #define EMIF_REG_ZQ_DUALCALEN_SHIFT			29
426 #define EMIF_REG_ZQ_DUALCALEN_MASK			(1 << 29)
427 #define EMIF_REG_ZQ_SFEXITEN_SHIFT			28
428 #define EMIF_REG_ZQ_SFEXITEN_MASK			(1 << 28)
429 #define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT		18
430 #define EMIF_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
431 #define EMIF_REG_ZQ_ZQCL_MULT_SHIFT			16
432 #define EMIF_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
433 #define EMIF_REG_ZQ_REFINTERVAL_SHIFT		0
434 #define EMIF_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
435 
436 /* TEMP_ALERT_CONFIG */
437 #define EMIF_REG_TA_CS1EN_SHIFT			31
438 #define EMIF_REG_TA_CS1EN_MASK			(1 << 31)
439 #define EMIF_REG_TA_CS0EN_SHIFT			30
440 #define EMIF_REG_TA_CS0EN_MASK			(1 << 30)
441 #define EMIF_REG_TA_SFEXITEN_SHIFT			28
442 #define EMIF_REG_TA_SFEXITEN_MASK			(1 << 28)
443 #define EMIF_REG_TA_DEVWDT_SHIFT			26
444 #define EMIF_REG_TA_DEVWDT_MASK			(0x3 << 26)
445 #define EMIF_REG_TA_DEVCNT_SHIFT			24
446 #define EMIF_REG_TA_DEVCNT_MASK			(0x3 << 24)
447 #define EMIF_REG_TA_REFINTERVAL_SHIFT		0
448 #define EMIF_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
449 
450 /* OCP_ERR_LOG */
451 #define EMIF_REG_MADDRSPACE_SHIFT			14
452 #define EMIF_REG_MADDRSPACE_MASK			(0x3 << 14)
453 #define EMIF_REG_MBURSTSEQ_SHIFT			11
454 #define EMIF_REG_MBURSTSEQ_MASK			(0x7 << 11)
455 #define EMIF_REG_MCMD_SHIFT				8
456 #define EMIF_REG_MCMD_MASK				(0x7 << 8)
457 #define EMIF_REG_MCONNID_SHIFT			0
458 #define EMIF_REG_MCONNID_MASK			(0xff << 0)
459 
460 /* DDR_PHY_CTRL_1 */
461 #define EMIF_REG_DDR_PHY_CTRL_1_SHIFT		4
462 #define EMIF_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
463 #define EMIF_REG_READ_LATENCY_SHIFT			0
464 #define EMIF_REG_READ_LATENCY_MASK			(0xf << 0)
465 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
466 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
467 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
468 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
469 
470 /* DDR_PHY_CTRL_1_SHDW */
471 #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
472 #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
473 #define EMIF_REG_READ_LATENCY_SHDW_SHIFT		0
474 #define EMIF_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
475 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
476 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
477 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
478 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
479 
480 /* DDR_PHY_CTRL_2 */
481 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT		0
482 #define EMIF_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
483 
484 /*EMIF_READ_WRITE_LEVELING_CONTROL*/
485 #define EMIF_REG_RDWRLVLFULL_START_SHIFT	31
486 #define EMIF_REG_RDWRLVLFULL_START_MASK		(1 << 31)
487 #define EMIF_REG_RDWRLVLINC_PRE_SHIFT		24
488 #define EMIF_REG_RDWRLVLINC_PRE_MASK		(0x7F << 24)
489 #define EMIF_REG_RDLVLINC_INT_SHIFT		16
490 #define EMIF_REG_RDLVLINC_INT_MASK		(0xFF << 16)
491 #define EMIF_REG_RDLVLGATEINC_INT_SHIFT		8
492 #define EMIF_REG_RDLVLGATEINC_INT_MASK		(0xFF << 8)
493 #define EMIF_REG_WRLVLINC_INT_SHIFT		0
494 #define EMIF_REG_WRLVLINC_INT_MASK		(0xFF << 0)
495 
496 /*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
497 #define EMIF_REG_RDWRLVL_EN_SHIFT		31
498 #define EMIF_REG_RDWRLVL_EN_MASK		(1 << 31)
499 #define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT	24
500 #define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK	(0x7F << 24)
501 #define EMIF_REG_RDLVLINC_RMP_INT_SHIFT		16
502 #define EMIF_REG_RDLVLINC_RMP_INT_MASK		(0xFF << 16)
503 #define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT	8
504 #define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK	(0xFF << 8)
505 #define EMIF_REG_WRLVLINC_RMP_INT_SHIFT		0
506 #define EMIF_REG_WRLVLINC_RMP_INT_MASK		(0xFF << 0)
507 
508 /*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
509 #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT	0
510 #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK	(0x1FFF << 0)
511 
512 /*Leveling Fields */
513 #define DDR3_WR_LVL_INT		0x73
514 #define DDR3_RD_LVL_INT		0x33
515 #define DDR3_RD_LVL_GATE_INT	0x59
516 #define RD_RW_LVL_INC_PRE	0x0
517 #define DDR3_FULL_LVL		(1 << EMIF_REG_RDWRLVL_EN_SHIFT)
518 
519 #define DDR3_INC_LVL	((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT)   \
520 		| (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
521 		| (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT)      \
522 		| (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
523 
524 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES	0x0000C1A7
525 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES	0x000001A7
526 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
527 
528 /* DMM */
529 #define DMM_BASE			0x4E000040
530 
531 /* Memory Adapter */
532 #define MA_BASE				0x482AF040
533 
534 /* DMM_LISA_MAP */
535 #define EMIF_SYS_ADDR_SHIFT		24
536 #define EMIF_SYS_ADDR_MASK		(0xff << 24)
537 #define EMIF_SYS_SIZE_SHIFT		20
538 #define EMIF_SYS_SIZE_MASK		(0x7 << 20)
539 #define EMIF_SDRC_INTL_SHIFT	18
540 #define EMIF_SDRC_INTL_MASK		(0x3 << 18)
541 #define EMIF_SDRC_ADDRSPC_SHIFT	16
542 #define EMIF_SDRC_ADDRSPC_MASK	(0x3 << 16)
543 #define EMIF_SDRC_MAP_SHIFT		8
544 #define EMIF_SDRC_MAP_MASK		(0x3 << 8)
545 #define EMIF_SDRC_ADDR_SHIFT	0
546 #define EMIF_SDRC_ADDR_MASK		(0xff << 0)
547 
548 /* DMM_LISA_MAP fields */
549 #define DMM_SDRC_MAP_UNMAPPED		0
550 #define DMM_SDRC_MAP_EMIF1_ONLY		1
551 #define DMM_SDRC_MAP_EMIF2_ONLY		2
552 #define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
553 
554 #define DMM_SDRC_INTL_NONE		0
555 #define DMM_SDRC_INTL_128B		1
556 #define DMM_SDRC_INTL_256B		2
557 #define DMM_SDRC_INTL_512		3
558 
559 #define DMM_SDRC_ADDR_SPC_SDRAM		0
560 #define DMM_SDRC_ADDR_SPC_NVM		1
561 #define DMM_SDRC_ADDR_SPC_INVALID	2
562 
563 #define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
564 	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
565 	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
566 	(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
567 	(CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
568 
569 #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
570 	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
571 	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
572 	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
573 
574 #define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
575 	(DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
576 	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
577 	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
578 
579 /* Trap for invalid TILER PAT entries */
580 #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
581 	(0  << EMIF_SDRC_ADDR_SHIFT) |\
582 	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
583 	(DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
584 	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
585 	(0xFF << EMIF_SYS_ADDR_SHIFT))
586 
587 #define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
588 
589 /* Reg mapping structure */
590 struct emif_reg_struct {
591 	u32 emif_mod_id_rev;
592 	u32 emif_status;
593 	u32 emif_sdram_config;
594 	u32 emif_lpddr2_nvm_config;
595 	u32 emif_sdram_ref_ctrl;
596 	u32 emif_sdram_ref_ctrl_shdw;
597 	u32 emif_sdram_tim_1;
598 	u32 emif_sdram_tim_1_shdw;
599 	u32 emif_sdram_tim_2;
600 	u32 emif_sdram_tim_2_shdw;
601 	u32 emif_sdram_tim_3;
602 	u32 emif_sdram_tim_3_shdw;
603 	u32 emif_lpddr2_nvm_tim;
604 	u32 emif_lpddr2_nvm_tim_shdw;
605 	u32 emif_pwr_mgmt_ctrl;
606 	u32 emif_pwr_mgmt_ctrl_shdw;
607 	u32 emif_lpddr2_mode_reg_data;
608 	u32 padding1[1];
609 	u32 emif_lpddr2_mode_reg_data_es2;
610 	u32 padding11[1];
611 	u32 emif_lpddr2_mode_reg_cfg;
612 	u32 emif_l3_config;
613 	u32 emif_l3_cfg_val_1;
614 	u32 emif_l3_cfg_val_2;
615 	u32 emif_iodft_tlgc;
616 	u32 padding2[7];
617 	u32 emif_perf_cnt_1;
618 	u32 emif_perf_cnt_2;
619 	u32 emif_perf_cnt_cfg;
620 	u32 emif_perf_cnt_sel;
621 	u32 emif_perf_cnt_tim;
622 	u32 padding3;
623 	u32 emif_read_idlectrl;
624 	u32 emif_read_idlectrl_shdw;
625 	u32 padding4;
626 	u32 emif_irqstatus_raw_sys;
627 	u32 emif_irqstatus_raw_ll;
628 	u32 emif_irqstatus_sys;
629 	u32 emif_irqstatus_ll;
630 	u32 emif_irqenable_set_sys;
631 	u32 emif_irqenable_set_ll;
632 	u32 emif_irqenable_clr_sys;
633 	u32 emif_irqenable_clr_ll;
634 	u32 padding5;
635 	u32 emif_zq_config;
636 	u32 emif_temp_alert_config;
637 	u32 emif_l3_err_log;
638 	u32 emif_rd_wr_lvl_rmp_win;
639 	u32 emif_rd_wr_lvl_rmp_ctl;
640 	u32 emif_rd_wr_lvl_ctl;
641 	u32 padding6[1];
642 	u32 emif_ddr_phy_ctrl_1;
643 	u32 emif_ddr_phy_ctrl_1_shdw;
644 	u32 emif_ddr_phy_ctrl_2;
645 	u32 padding7[4];
646 	u32 emif_prio_class_serv_map;
647 	u32 emif_connect_id_serv_1_map;
648 	u32 emif_connect_id_serv_2_map;
649 	u32 padding8[5];
650 	u32 emif_rd_wr_exec_thresh;
651 	u32 emif_cos_config;
652 	u32 padding9[6];
653 	u32 emif_ddr_phy_status[21];
654 	u32 padding10[27];
655 	u32 emif_ddr_ext_phy_ctrl_1;
656 	u32 emif_ddr_ext_phy_ctrl_1_shdw;
657 	u32 emif_ddr_ext_phy_ctrl_2;
658 	u32 emif_ddr_ext_phy_ctrl_2_shdw;
659 	u32 emif_ddr_ext_phy_ctrl_3;
660 	u32 emif_ddr_ext_phy_ctrl_3_shdw;
661 	u32 emif_ddr_ext_phy_ctrl_4;
662 	u32 emif_ddr_ext_phy_ctrl_4_shdw;
663 	u32 emif_ddr_ext_phy_ctrl_5;
664 	u32 emif_ddr_ext_phy_ctrl_5_shdw;
665 	u32 emif_ddr_ext_phy_ctrl_6;
666 	u32 emif_ddr_ext_phy_ctrl_6_shdw;
667 	u32 emif_ddr_ext_phy_ctrl_7;
668 	u32 emif_ddr_ext_phy_ctrl_7_shdw;
669 	u32 emif_ddr_ext_phy_ctrl_8;
670 	u32 emif_ddr_ext_phy_ctrl_8_shdw;
671 	u32 emif_ddr_ext_phy_ctrl_9;
672 	u32 emif_ddr_ext_phy_ctrl_9_shdw;
673 	u32 emif_ddr_ext_phy_ctrl_10;
674 	u32 emif_ddr_ext_phy_ctrl_10_shdw;
675 	u32 emif_ddr_ext_phy_ctrl_11;
676 	u32 emif_ddr_ext_phy_ctrl_11_shdw;
677 	u32 emif_ddr_ext_phy_ctrl_12;
678 	u32 emif_ddr_ext_phy_ctrl_12_shdw;
679 	u32 emif_ddr_ext_phy_ctrl_13;
680 	u32 emif_ddr_ext_phy_ctrl_13_shdw;
681 	u32 emif_ddr_ext_phy_ctrl_14;
682 	u32 emif_ddr_ext_phy_ctrl_14_shdw;
683 	u32 emif_ddr_ext_phy_ctrl_15;
684 	u32 emif_ddr_ext_phy_ctrl_15_shdw;
685 	u32 emif_ddr_ext_phy_ctrl_16;
686 	u32 emif_ddr_ext_phy_ctrl_16_shdw;
687 	u32 emif_ddr_ext_phy_ctrl_17;
688 	u32 emif_ddr_ext_phy_ctrl_17_shdw;
689 	u32 emif_ddr_ext_phy_ctrl_18;
690 	u32 emif_ddr_ext_phy_ctrl_18_shdw;
691 	u32 emif_ddr_ext_phy_ctrl_19;
692 	u32 emif_ddr_ext_phy_ctrl_19_shdw;
693 	u32 emif_ddr_ext_phy_ctrl_20;
694 	u32 emif_ddr_ext_phy_ctrl_20_shdw;
695 	u32 emif_ddr_ext_phy_ctrl_21;
696 	u32 emif_ddr_ext_phy_ctrl_21_shdw;
697 	u32 emif_ddr_ext_phy_ctrl_22;
698 	u32 emif_ddr_ext_phy_ctrl_22_shdw;
699 	u32 emif_ddr_ext_phy_ctrl_23;
700 	u32 emif_ddr_ext_phy_ctrl_23_shdw;
701 	u32 emif_ddr_ext_phy_ctrl_24;
702 	u32 emif_ddr_ext_phy_ctrl_24_shdw;
703 	u32 padding[22];
704 	u32 emif_ddr_fifo_misaligned_clear_1;
705 	u32 emif_ddr_fifo_misaligned_clear_2;
706 };
707 
708 struct dmm_lisa_map_regs {
709 	u32 dmm_lisa_map_0;
710 	u32 dmm_lisa_map_1;
711 	u32 dmm_lisa_map_2;
712 	u32 dmm_lisa_map_3;
713 	u8 is_ma_present;
714 };
715 
716 #define CS0	0
717 #define CS1	1
718 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
719 #define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
720 
721 /*
722  * The period of DDR clk is represented as numerator and denominator for
723  * better accuracy in integer based calculations. However, if the numerator
724  * and denominator are very huge there may be chances of overflow in
725  * calculations. So, as a trade-off keep denominator(and consequently
726  * numerator) within a limit sacrificing some accuracy - but not much
727  * If denominator and numerator are already small (such as at 400 MHz)
728  * no adjustment is needed
729  */
730 #define EMIF_PERIOD_DEN_LIMIT	1000
731 /*
732  * Maximum number of different frequencies supported by EMIF driver
733  * Determines the number of entries in the pointer array for register
734  * cache
735  */
736 #define EMIF_MAX_NUM_FREQUENCIES	6
737 /*
738  * Indices into the Addressing Table array.
739  * One entry each for all the different types of devices with different
740  * addressing schemes
741  */
742 #define ADDR_TABLE_INDEX64M	0
743 #define ADDR_TABLE_INDEX128M	1
744 #define ADDR_TABLE_INDEX256M	2
745 #define ADDR_TABLE_INDEX512M	3
746 #define ADDR_TABLE_INDEX1GS4	4
747 #define ADDR_TABLE_INDEX2GS4	5
748 #define ADDR_TABLE_INDEX4G	6
749 #define ADDR_TABLE_INDEX8G	7
750 #define ADDR_TABLE_INDEX1GS2	8
751 #define ADDR_TABLE_INDEX2GS2	9
752 #define ADDR_TABLE_INDEXMAX	10
753 
754 /* Number of Row bits */
755 #define ROW_9  0
756 #define ROW_10 1
757 #define ROW_11 2
758 #define ROW_12 3
759 #define ROW_13 4
760 #define ROW_14 5
761 #define ROW_15 6
762 #define ROW_16 7
763 
764 /* Number of Column bits */
765 #define COL_8   0
766 #define COL_9   1
767 #define COL_10  2
768 #define COL_11  3
769 #define COL_7   4 /*Not supported by OMAP included for completeness */
770 
771 /* Number of Banks*/
772 #define BANKS1 0
773 #define BANKS2 1
774 #define BANKS4 2
775 #define BANKS8 3
776 
777 /* Refresh rate in micro seconds x 10 */
778 #define T_REFI_15_6	156
779 #define T_REFI_7_8	78
780 #define T_REFI_3_9	39
781 
782 #define EBANK_CS1_DIS	0
783 #define EBANK_CS1_EN	1
784 
785 /* Read Latency used by the device at reset */
786 #define RL_BOOT		3
787 /* Read Latency for the highest frequency you want to use */
788 #ifdef CONFIG_OMAP54XX
789 #define RL_FINAL	8
790 #else
791 #define RL_FINAL	6
792 #endif
793 
794 
795 /* Interleaving policies at EMIF level- between banks and Chip Selects */
796 #define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
797 #define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
798 
799 /*
800  * Interleaving policy to be used
801  * Currently set to MAX interleaving for better performance
802  */
803 #define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
804 
805 /* State of the core voltage:
806  * This is important for some parameters such as read idle control and
807  * ZQ calibration timings. Timings are much stricter when voltage ramp
808  * is happening compared to when the voltage is stable.
809  * We need to calculate two sets of values for these parameters and use
810  * them accordingly
811  */
812 #define LPDDR2_VOLTAGE_STABLE	0
813 #define LPDDR2_VOLTAGE_RAMPING	1
814 
815 /* Length of the forced read idle period in terms of cycles */
816 #define EMIF_REG_READ_IDLE_LEN_VAL	5
817 
818 /* Interval between forced 'read idles' */
819 /* To be used when voltage is changed for DPS/DVFS - 1us */
820 #define READ_IDLE_INTERVAL_DVFS		(1*1000)
821 /*
822  * To be used when voltage is not scaled except by Smart Reflex
823  * 50us - or maximum value will do
824  */
825 #define READ_IDLE_INTERVAL_NORMAL	(50*1000)
826 
827 
828 /*
829  * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
830  * be enough. This shoule be enough also in the case when voltage is changing
831  * due to smart-reflex.
832  */
833 #define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
834 /*
835  * If voltage is changing due to DVFS ZQCS should be performed more
836  * often(every 50us)
837  */
838 #define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
839 
840 /* The interval between ZQCL commands as a multiple of ZQCS interval */
841 #define REG_ZQ_ZQCL_MULT		4
842 /* The interval between ZQINIT commands as a multiple of ZQCL interval */
843 #define REG_ZQ_ZQINIT_MULT		3
844 /* Enable ZQ Calibration on exiting Self-refresh */
845 #define REG_ZQ_SFEXITEN_ENABLE		1
846 /*
847  * ZQ Calibration simultaneously on both chip-selects:
848  * Needs one calibration resistor per CS
849  * None of the boards that we know of have this capability
850  * So disabled by default
851  */
852 #define REG_ZQ_DUALCALEN_DISABLE	0
853 /*
854  * Enable ZQ Calibration by default on CS0. If we are asked to program
855  * the EMIF there will be something connected to CS0 for sure
856  */
857 #define REG_ZQ_CS0EN_ENABLE		1
858 
859 /* EMIF_PWR_MGMT_CTRL register */
860 /* Low power modes */
861 #define LP_MODE_DISABLE		0
862 #define LP_MODE_CLOCK_STOP	1
863 #define LP_MODE_SELF_REFRESH	2
864 #define LP_MODE_PWR_DN		3
865 
866 /* REG_DPD_EN */
867 #define DPD_DISABLE	0
868 #define DPD_ENABLE	1
869 
870 /* Maximum delay before Low Power Modes */
871 #define REG_CS_TIM		0x0
872 #define REG_SR_TIM		0x0
873 #define REG_PD_TIM		0x0
874 
875 
876 /* EMIF_PWR_MGMT_CTRL register */
877 #define EMIF_PWR_MGMT_CTRL (\
878 	((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
879 	((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
880 	((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
881 	((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
882 			& EMIF_REG_LP_MODE_MASK) |\
883 	((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
884 			& EMIF_REG_DPD_EN_MASK))\
885 
886 #define EMIF_PWR_MGMT_CTRL_SHDW (\
887 	((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
888 			& EMIF_REG_CS_TIM_SHDW_MASK) |\
889 	((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
890 			& EMIF_REG_SR_TIM_SHDW_MASK) |\
891 	((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
892 			& EMIF_REG_PD_TIM_SHDW_MASK))
893 
894 /* EMIF_L3_CONFIG register value */
895 #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0	0x0A0000FF
896 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
897 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0	0x0A500000
898 
899 /*
900  * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
901  * All these fields have magic values dependent on frequency and
902  * determined by PHY and DLL integration with EMIF. Setting the magic
903  * values suggested by hw team.
904  */
905 #define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
906 #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
907 #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
908 #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
909 
910 /*
911 * MR1 value:
912 * Burst length	: 8
913 * Burst type	: sequential
914 * Wrap		: enabled
915 * nWR		: 3(default). EMIF does not do pre-charge.
916 *		: So nWR is don't care
917 */
918 #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
919 #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8	0xc3
920 
921 /* MR2 */
922 #define MR2_RL3_WL1			1
923 #define MR2_RL4_WL2			2
924 #define MR2_RL5_WL2			3
925 #define MR2_RL6_WL3			4
926 
927 /* MR10: ZQ calibration codes */
928 #define MR10_ZQ_ZQCS		0x56
929 #define MR10_ZQ_ZQCL		0xAB
930 #define MR10_ZQ_ZQINIT		0xFF
931 #define MR10_ZQ_ZQRESET		0xC3
932 
933 /* TEMP_ALERT_CONFIG */
934 #define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
935 #define TEMP_ALERT_CONFIG_DEVCT_1	0
936 #define TEMP_ALERT_CONFIG_DEVWDT_32	2
937 
938 /* MR16 value: refresh full array(no partial array self refresh) */
939 #define MR16_REF_FULL_ARRAY	0
940 
941 /*
942  * Maximum number of entries we keep in our array of timing tables
943  * We need not keep all the speed bins supported by the device
944  * We need to keep timing tables for only the speed bins that we
945  * are interested in
946  */
947 #define MAX_NUM_SPEEDBINS	4
948 
949 /* LPDDR2 Densities */
950 #define LPDDR2_DENSITY_64Mb	0
951 #define LPDDR2_DENSITY_128Mb	1
952 #define LPDDR2_DENSITY_256Mb	2
953 #define LPDDR2_DENSITY_512Mb	3
954 #define LPDDR2_DENSITY_1Gb	4
955 #define LPDDR2_DENSITY_2Gb	5
956 #define LPDDR2_DENSITY_4Gb	6
957 #define LPDDR2_DENSITY_8Gb	7
958 #define LPDDR2_DENSITY_16Gb	8
959 #define LPDDR2_DENSITY_32Gb	9
960 
961 /* LPDDR2 type */
962 #define	LPDDR2_TYPE_S4	0
963 #define	LPDDR2_TYPE_S2	1
964 #define	LPDDR2_TYPE_NVM	2
965 
966 /* LPDDR2 IO width */
967 #define	LPDDR2_IO_WIDTH_32	0
968 #define	LPDDR2_IO_WIDTH_16	1
969 #define	LPDDR2_IO_WIDTH_8	2
970 
971 /* Mode register numbers */
972 #define LPDDR2_MR0	0
973 #define LPDDR2_MR1	1
974 #define LPDDR2_MR2	2
975 #define LPDDR2_MR3	3
976 #define LPDDR2_MR4	4
977 #define LPDDR2_MR5	5
978 #define LPDDR2_MR6	6
979 #define LPDDR2_MR7	7
980 #define LPDDR2_MR8	8
981 #define LPDDR2_MR9	9
982 #define LPDDR2_MR10	10
983 #define LPDDR2_MR11	11
984 #define LPDDR2_MR16	16
985 #define LPDDR2_MR17	17
986 #define LPDDR2_MR18	18
987 
988 /* MR0 */
989 #define LPDDR2_MR0_DAI_SHIFT	0
990 #define LPDDR2_MR0_DAI_MASK	1
991 #define LPDDR2_MR0_DI_SHIFT	1
992 #define LPDDR2_MR0_DI_MASK	(1 << 1)
993 #define LPDDR2_MR0_DNVI_SHIFT	2
994 #define LPDDR2_MR0_DNVI_MASK	(1 << 2)
995 
996 /* MR4 */
997 #define MR4_SDRAM_REF_RATE_SHIFT	0
998 #define MR4_SDRAM_REF_RATE_MASK		7
999 #define MR4_TUF_SHIFT			7
1000 #define MR4_TUF_MASK			(1 << 7)
1001 
1002 /* MR4 SDRAM Refresh Rate field values */
1003 #define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
1004 #define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
1005 #define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
1006 #define SDRAM_TEMP_NOMINAL				0x3
1007 #define SDRAM_TEMP_RESERVED_4				0x4
1008 #define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
1009 #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
1010 #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
1011 
1012 #define LPDDR2_MANUFACTURER_SAMSUNG	1
1013 #define LPDDR2_MANUFACTURER_QIMONDA	2
1014 #define LPDDR2_MANUFACTURER_ELPIDA	3
1015 #define LPDDR2_MANUFACTURER_ETRON	4
1016 #define LPDDR2_MANUFACTURER_NANYA	5
1017 #define LPDDR2_MANUFACTURER_HYNIX	6
1018 #define LPDDR2_MANUFACTURER_MOSEL	7
1019 #define LPDDR2_MANUFACTURER_WINBOND	8
1020 #define LPDDR2_MANUFACTURER_ESMT	9
1021 #define LPDDR2_MANUFACTURER_SPANSION 11
1022 #define LPDDR2_MANUFACTURER_SST		12
1023 #define LPDDR2_MANUFACTURER_ZMOS	13
1024 #define LPDDR2_MANUFACTURER_INTEL	14
1025 #define LPDDR2_MANUFACTURER_NUMONYX	254
1026 #define LPDDR2_MANUFACTURER_MICRON	255
1027 
1028 /* MR8 register fields */
1029 #define MR8_TYPE_SHIFT		0x0
1030 #define MR8_TYPE_MASK		0x3
1031 #define MR8_DENSITY_SHIFT	0x2
1032 #define MR8_DENSITY_MASK	(0xF << 0x2)
1033 #define MR8_IO_WIDTH_SHIFT	0x6
1034 #define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
1035 
1036 /* SDRAM TYPE */
1037 #define EMIF_SDRAM_TYPE_DDR2	0x2
1038 #define EMIF_SDRAM_TYPE_DDR3	0x3
1039 #define EMIF_SDRAM_TYPE_LPDDR2	0x4
1040 
1041 struct lpddr2_addressing {
1042 	u8	num_banks;
1043 	u8	t_REFI_us_x10;
1044 	u8	row_sz[2]; /* One entry each for x32 and x16 */
1045 	u8	col_sz[2]; /* One entry each for x32 and x16 */
1046 };
1047 
1048 /* Structure for timings from the DDR datasheet */
1049 struct lpddr2_ac_timings {
1050 	u32 max_freq;
1051 	u8 RL;
1052 	u8 tRPab;
1053 	u8 tRCD;
1054 	u8 tWR;
1055 	u8 tRASmin;
1056 	u8 tRRD;
1057 	u8 tWTRx2;
1058 	u8 tXSR;
1059 	u8 tXPx2;
1060 	u8 tRFCab;
1061 	u8 tRTPx2;
1062 	u8 tCKE;
1063 	u8 tCKESR;
1064 	u8 tZQCS;
1065 	u32 tZQCL;
1066 	u32 tZQINIT;
1067 	u8 tDQSCKMAXx2;
1068 	u8 tRASmax;
1069 	u8 tFAW;
1070 
1071 };
1072 
1073 /*
1074  * Min tCK values for some of the parameters:
1075  * If the calculated clock cycles for the respective parameter is
1076  * less than the corresponding min tCK value, we need to set the min
1077  * tCK value. This may happen at lower frequencies.
1078  */
1079 struct lpddr2_min_tck {
1080 	u32 tRL;
1081 	u32 tRP_AB;
1082 	u32 tRCD;
1083 	u32 tWR;
1084 	u32 tRAS_MIN;
1085 	u32 tRRD;
1086 	u32 tWTR;
1087 	u32 tXP;
1088 	u32 tRTP;
1089 	u8  tCKE;
1090 	u32 tCKESR;
1091 	u32 tFAW;
1092 };
1093 
1094 struct lpddr2_device_details {
1095 	u8	type;
1096 	u8	density;
1097 	u8	io_width;
1098 	u8	manufacturer;
1099 };
1100 
1101 struct lpddr2_device_timings {
1102 	const struct lpddr2_ac_timings **ac_timings;
1103 	const struct lpddr2_min_tck *min_tck;
1104 };
1105 
1106 /* Details of the devices connected to each chip-select of an EMIF instance */
1107 struct emif_device_details {
1108 	const struct lpddr2_device_details *cs0_device_details;
1109 	const struct lpddr2_device_details *cs1_device_details;
1110 	const struct lpddr2_device_timings *cs0_device_timings;
1111 	const struct lpddr2_device_timings *cs1_device_timings;
1112 };
1113 
1114 /*
1115  * Structure containing shadow of important registers in EMIF
1116  * The calculation function fills in this structure to be later used for
1117  * initialization and DVFS
1118  */
1119 struct emif_regs {
1120 	u32 freq;
1121 	u32 sdram_config_init;
1122 	u32 sdram_config;
1123 	u32 sdram_config2;
1124 	u32 ref_ctrl;
1125 	u32 sdram_tim1;
1126 	u32 sdram_tim2;
1127 	u32 sdram_tim3;
1128 	u32 read_idle_ctrl;
1129 	u32 zq_config;
1130 	u32 temp_alert_config;
1131 	u32 emif_ddr_phy_ctlr_1_init;
1132 	u32 emif_ddr_phy_ctlr_1;
1133 	u32 emif_ddr_ext_phy_ctrl_1;
1134 	u32 emif_ddr_ext_phy_ctrl_2;
1135 	u32 emif_ddr_ext_phy_ctrl_3;
1136 	u32 emif_ddr_ext_phy_ctrl_4;
1137 	u32 emif_ddr_ext_phy_ctrl_5;
1138 	u32 emif_rd_wr_lvl_rmp_win;
1139 	u32 emif_rd_wr_lvl_rmp_ctl;
1140 	u32 emif_rd_wr_lvl_ctl;
1141 	u32 emif_rd_wr_exec_thresh;
1142 	u32 emif_prio_class_serv_map;
1143 	u32 emif_connect_id_serv_1_map;
1144 	u32 emif_connect_id_serv_2_map;
1145 	u32 emif_cos_config;
1146 };
1147 
1148 struct lpddr2_mr_regs {
1149 	s8 mr1;
1150 	s8 mr2;
1151 	s8 mr3;
1152 	s8 mr10;
1153 	s8 mr16;
1154 };
1155 
1156 struct read_write_regs {
1157 	u32 read_reg;
1158 	u32 write_reg;
1159 };
1160 
1161 static inline u32 get_emif_rev(u32 base)
1162 {
1163 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1164 
1165 	return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
1166 		>> EMIF_REG_MAJOR_REVISION_SHIFT;
1167 }
1168 
1169 /*
1170  * Get SDRAM type connected to EMIF.
1171  * Assuming similar SDRAM parts are connected to both EMIF's
1172  * which is typically the case. So it is sufficient to get
1173  * SDRAM type from EMIF1.
1174  */
1175 static inline u32 emif_sdram_type(void)
1176 {
1177 	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
1178 
1179 	return (readl(&emif->emif_sdram_config) &
1180 		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
1181 }
1182 
1183 /* assert macros */
1184 #if defined(DEBUG)
1185 #define emif_assert(c)	({ if (!(c)) for (;;); })
1186 #else
1187 #define emif_assert(c)	({ if (0) hang(); })
1188 #endif
1189 
1190 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1191 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
1192 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
1193 #else
1194 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1195 			struct lpddr2_device_details *lpddr2_dev_details);
1196 void emif_get_device_timings(u32 emif_nr,
1197 		const struct lpddr2_device_timings **cs0_device_timings,
1198 		const struct lpddr2_device_timings **cs1_device_timings);
1199 #endif
1200 
1201 void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
1202 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
1203 
1204 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1205 extern u32 *const T_num;
1206 extern u32 *const T_den;
1207 #endif
1208 
1209 void config_data_eye_leveling_samples(u32 emif_base);
1210 u32 emif_sdram_type(void);
1211 const struct read_write_regs *get_bug_regs(u32 *iterations);
1212 #endif
1213