1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 */ 24 25 #ifndef _ASM_CACHE_H 26 #define _ASM_CACHE_H 27 28 #include <asm/system.h> 29 30 /* 31 * Invalidate L2 Cache using co-proc instruction 32 */ 33 static inline void invalidate_l2_cache(void) 34 { 35 unsigned int val=0; 36 37 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 38 : : "r" (val) : "cc"); 39 isb(); 40 } 41 42 void l2_cache_enable(void); 43 void l2_cache_disable(void); 44 void set_section_dcache(int section, enum dcache_option option); 45 46 void dram_bank_mmu_setup(int bank); 47 /* 48 * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We 49 * use that value for aligning DMA buffers unless the board config has specified 50 * an alternate cache line size. 51 */ 52 #ifdef CONFIG_SYS_CACHELINE_SIZE 53 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 54 #else 55 #define ARCH_DMA_MINALIGN 64 56 #endif 57 58 #endif /* _ASM_CACHE_H */ 59