1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _ASM_CACHE_H 10 #define _ASM_CACHE_H 11 12 #include <asm/system.h> 13 14 #ifndef CONFIG_ARM64 15 16 /* 17 * Invalidate L2 Cache using co-proc instruction 18 */ 19 #ifdef CONFIG_SYS_THUMB_BUILD 20 void invalidate_l2_cache(void); 21 #else 22 static inline void invalidate_l2_cache(void) 23 { 24 unsigned int val=0; 25 26 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 27 : : "r" (val) : "cc"); 28 isb(); 29 } 30 #endif 31 32 int check_cache_range(unsigned long start, unsigned long stop); 33 34 void l2_cache_enable(void); 35 void l2_cache_disable(void); 36 void set_section_dcache(int section, enum dcache_option option); 37 38 void arm_init_before_mmu(void); 39 void arm_init_domains(void); 40 void cpu_cache_initialization(void); 41 void dram_bank_mmu_setup(int bank); 42 43 #endif 44 45 /* 46 * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We 47 * use that value for aligning DMA buffers unless the board config has specified 48 * an alternate cache line size. 49 */ 50 #ifdef CONFIG_SYS_CACHELINE_SIZE 51 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 52 #else 53 #define ARCH_DMA_MINALIGN 64 54 #endif 55 56 #endif /* _ASM_CACHE_H */ 57