1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _ASM_CACHE_H 10 #define _ASM_CACHE_H 11 12 #include <asm/system.h> 13 14 /* 15 * Invalidate L2 Cache using co-proc instruction 16 */ 17 static inline void invalidate_l2_cache(void) 18 { 19 unsigned int val=0; 20 21 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 22 : : "r" (val) : "cc"); 23 isb(); 24 } 25 26 void l2_cache_enable(void); 27 void l2_cache_disable(void); 28 void set_section_dcache(int section, enum dcache_option option); 29 30 void dram_bank_mmu_setup(int bank); 31 /* 32 * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We 33 * use that value for aligning DMA buffers unless the board config has specified 34 * an alternate cache line size. 35 */ 36 #ifdef CONFIG_SYS_CACHELINE_SIZE 37 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 38 #else 39 #define ARCH_DMA_MINALIGN 64 40 #endif 41 42 #endif /* _ASM_CACHE_H */ 43