1 /* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARMV8_MMU_H_ 9 #define _ASM_ARMV8_MMU_H_ 10 11 /***************************************************************/ 12 /* 13 * The following definitions are related each other, shoud be 14 * calculated specifically. 15 */ 16 17 #define VA_BITS CONFIG_SYS_VA_BITS 18 #define PTE_BLOCK_BITS CONFIG_SYS_PTL2_BITS 19 20 /* 21 * block/section address mask and size definitions. 22 */ 23 24 /* PAGE_SHIFT determines the page size */ 25 #undef PAGE_SIZE 26 #define PAGE_SHIFT 12 27 #define PAGE_SIZE (1 << PAGE_SHIFT) 28 #define PAGE_MASK (~(PAGE_SIZE-1)) 29 30 /***************************************************************/ 31 32 /* 33 * Memory types 34 */ 35 #define MT_DEVICE_NGNRNE 0 36 #define MT_DEVICE_NGNRE 1 37 #define MT_DEVICE_GRE 2 38 #define MT_NORMAL_NC 3 39 #define MT_NORMAL 4 40 41 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ 42 (0x04 << (MT_DEVICE_NGNRE * 8)) | \ 43 (0x0c << (MT_DEVICE_GRE * 8)) | \ 44 (0x44 << (MT_NORMAL_NC * 8)) | \ 45 (UL(0xff) << (MT_NORMAL * 8))) 46 47 /* 48 * Hardware page table definitions. 49 * 50 */ 51 52 #define PTE_TYPE_MASK (3 << 0) 53 #define PTE_TYPE_FAULT (0 << 0) 54 #define PTE_TYPE_TABLE (3 << 0) 55 #define PTE_TYPE_BLOCK (1 << 0) 56 57 #define PTE_TABLE_PXN (1UL << 59) 58 #define PTE_TABLE_XN (1UL << 60) 59 #define PTE_TABLE_AP (1UL << 61) 60 #define PTE_TABLE_NS (1UL << 63) 61 62 /* 63 * Block 64 */ 65 #define PTE_BLOCK_MEMTYPE(x) ((x) << 2) 66 #define PTE_BLOCK_NS (1 << 5) 67 #define PTE_BLOCK_NON_SHARE (0 << 8) 68 #define PTE_BLOCK_OUTER_SHARE (2 << 8) 69 #define PTE_BLOCK_INNER_SHARE (3 << 8) 70 #define PTE_BLOCK_AF (1 << 10) 71 #define PTE_BLOCK_NG (1 << 11) 72 #define PTE_BLOCK_PXN (UL(1) << 53) 73 #define PTE_BLOCK_UXN (UL(1) << 54) 74 75 /* 76 * AttrIndx[2:0] 77 */ 78 #define PMD_ATTRINDX(t) ((t) << 2) 79 #define PMD_ATTRINDX_MASK (7 << 2) 80 81 /* 82 * TCR flags. 83 */ 84 #define TCR_T0SZ(x) ((64 - (x)) << 0) 85 #define TCR_IRGN_NC (0 << 8) 86 #define TCR_IRGN_WBWA (1 << 8) 87 #define TCR_IRGN_WT (2 << 8) 88 #define TCR_IRGN_WBNWA (3 << 8) 89 #define TCR_IRGN_MASK (3 << 8) 90 #define TCR_ORGN_NC (0 << 10) 91 #define TCR_ORGN_WBWA (1 << 10) 92 #define TCR_ORGN_WT (2 << 10) 93 #define TCR_ORGN_WBNWA (3 << 10) 94 #define TCR_ORGN_MASK (3 << 10) 95 #define TCR_SHARED_NON (0 << 12) 96 #define TCR_SHARED_OUTER (2 << 12) 97 #define TCR_SHARED_INNER (3 << 12) 98 #define TCR_TG0_4K (0 << 14) 99 #define TCR_TG0_64K (1 << 14) 100 #define TCR_TG0_16K (2 << 14) 101 #define TCR_EPD1_DISABLE (1 << 23) 102 103 #define TCR_EL1_RSVD (1 << 31) 104 #define TCR_EL2_RSVD (1 << 31 | 1 << 23) 105 #define TCR_EL3_RSVD (1 << 31 | 1 << 23) 106 107 #ifndef __ASSEMBLY__ 108 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) 109 { 110 asm volatile("dsb sy"); 111 if (el == 1) { 112 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); 113 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); 114 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); 115 } else if (el == 2) { 116 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); 117 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); 118 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); 119 } else if (el == 3) { 120 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); 121 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); 122 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); 123 } else { 124 hang(); 125 } 126 asm volatile("isb"); 127 } 128 129 struct mm_region { 130 u64 virt; 131 u64 phys; 132 u64 size; 133 u64 attrs; 134 }; 135 136 extern struct mm_region *mem_map; 137 void setup_pgtables(void); 138 u64 get_tcr(int el, u64 *pips, u64 *pva_bits); 139 #endif 140 141 #endif /* _ASM_ARMV8_MMU_H_ */ 142