1 /* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARMV8_MMU_H_ 9 #define _ASM_ARMV8_MMU_H_ 10 11 #ifdef __ASSEMBLY__ 12 #define _AC(X, Y) X 13 #else 14 #define _AC(X, Y) (X##Y) 15 #endif 16 17 #define UL(x) _AC(x, UL) 18 19 /***************************************************************/ 20 /* 21 * The following definitions are related each other, shoud be 22 * calculated specifically. 23 */ 24 25 #define VA_BITS CONFIG_SYS_VA_BITS 26 #define PTE_BLOCK_BITS CONFIG_SYS_PTL2_BITS 27 28 /* 29 * block/section address mask and size definitions. 30 */ 31 32 /* PAGE_SHIFT determines the page size */ 33 #undef PAGE_SIZE 34 #define PAGE_SHIFT 12 35 #define PAGE_SIZE (1 << PAGE_SHIFT) 36 #define PAGE_MASK (~(PAGE_SIZE-1)) 37 38 /***************************************************************/ 39 40 /* 41 * Memory types 42 */ 43 #define MT_DEVICE_NGNRNE 0 44 #define MT_DEVICE_NGNRE 1 45 #define MT_DEVICE_GRE 2 46 #define MT_NORMAL_NC 3 47 #define MT_NORMAL 4 48 49 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ 50 (0x04 << (MT_DEVICE_NGNRE * 8)) | \ 51 (0x0c << (MT_DEVICE_GRE * 8)) | \ 52 (0x44 << (MT_NORMAL_NC * 8)) | \ 53 (UL(0xff) << (MT_NORMAL * 8))) 54 55 /* 56 * Hardware page table definitions. 57 * 58 */ 59 60 #define PTE_TYPE_MASK (3 << 0) 61 #define PTE_TYPE_FAULT (0 << 0) 62 #define PTE_TYPE_TABLE (3 << 0) 63 #define PTE_TYPE_BLOCK (1 << 0) 64 65 #define PTE_TABLE_PXN (1UL << 59) 66 #define PTE_TABLE_XN (1UL << 60) 67 #define PTE_TABLE_AP (1UL << 61) 68 #define PTE_TABLE_NS (1UL << 63) 69 70 /* 71 * Block 72 */ 73 #define PTE_BLOCK_MEMTYPE(x) ((x) << 2) 74 #define PTE_BLOCK_NS (1 << 5) 75 #define PTE_BLOCK_NON_SHARE (0 << 8) 76 #define PTE_BLOCK_OUTER_SHARE (2 << 8) 77 #define PTE_BLOCK_INNER_SHARE (3 << 8) 78 #define PTE_BLOCK_AF (1 << 10) 79 #define PTE_BLOCK_NG (1 << 11) 80 #define PTE_BLOCK_PXN (UL(1) << 53) 81 #define PTE_BLOCK_UXN (UL(1) << 54) 82 83 /* 84 * AttrIndx[2:0] 85 */ 86 #define PMD_ATTRINDX(t) ((t) << 2) 87 #define PMD_ATTRINDX_MASK (7 << 2) 88 89 /* 90 * TCR flags. 91 */ 92 #define TCR_T0SZ(x) ((64 - (x)) << 0) 93 #define TCR_IRGN_NC (0 << 8) 94 #define TCR_IRGN_WBWA (1 << 8) 95 #define TCR_IRGN_WT (2 << 8) 96 #define TCR_IRGN_WBNWA (3 << 8) 97 #define TCR_IRGN_MASK (3 << 8) 98 #define TCR_ORGN_NC (0 << 10) 99 #define TCR_ORGN_WBWA (1 << 10) 100 #define TCR_ORGN_WT (2 << 10) 101 #define TCR_ORGN_WBNWA (3 << 10) 102 #define TCR_ORGN_MASK (3 << 10) 103 #define TCR_SHARED_NON (0 << 12) 104 #define TCR_SHARED_OUTER (2 << 12) 105 #define TCR_SHARED_INNER (3 << 12) 106 #define TCR_TG0_4K (0 << 14) 107 #define TCR_TG0_64K (1 << 14) 108 #define TCR_TG0_16K (2 << 14) 109 #define TCR_EPD1_DISABLE (1 << 23) 110 111 #define TCR_EL1_RSVD (1 << 31) 112 #define TCR_EL2_RSVD (1 << 31 | 1 << 23) 113 #define TCR_EL3_RSVD (1 << 31 | 1 << 23) 114 115 #ifndef __ASSEMBLY__ 116 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) 117 { 118 asm volatile("dsb sy"); 119 if (el == 1) { 120 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); 121 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); 122 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); 123 } else if (el == 2) { 124 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); 125 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); 126 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); 127 } else if (el == 3) { 128 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); 129 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); 130 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); 131 } else { 132 hang(); 133 } 134 asm volatile("isb"); 135 } 136 137 struct mm_region { 138 u64 virt; 139 u64 phys; 140 u64 size; 141 u64 attrs; 142 }; 143 144 extern struct mm_region *mem_map; 145 void setup_pgtables(void); 146 u64 get_tcr(int el, u64 *pips, u64 *pva_bits); 147 #endif 148 149 #endif /* _ASM_ARMV8_MMU_H_ */ 150