1 /* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARMV8_MMU_H_ 9 #define _ASM_ARMV8_MMU_H_ 10 11 #ifdef __ASSEMBLY__ 12 #define _AC(X, Y) X 13 #else 14 #define _AC(X, Y) (X##Y) 15 #endif 16 17 #define UL(x) _AC(x, UL) 18 19 /***************************************************************/ 20 /* 21 * The following definitions are related each other, shoud be 22 * calculated specifically. 23 */ 24 25 #ifndef CONFIG_SYS_FULL_VA 26 #define VA_BITS (42) /* 42 bits virtual address */ 27 #else 28 #define VA_BITS CONFIG_SYS_VA_BITS 29 #define PTL2_BITS CONFIG_SYS_PTL2_BITS 30 #endif 31 32 /* PAGE_SHIFT determines the page size */ 33 #undef PAGE_SIZE 34 #define PAGE_SHIFT 16 35 #define PAGE_SIZE (1 << PAGE_SHIFT) 36 #define PAGE_MASK (~(PAGE_SIZE-1)) 37 38 /* 39 * block/section address mask and size definitions. 40 */ 41 #ifndef CONFIG_SYS_FULL_VA 42 #define SECTION_SHIFT 29 43 #define SECTION_SIZE (UL(1) << SECTION_SHIFT) 44 #define SECTION_MASK (~(SECTION_SIZE-1)) 45 #else 46 #define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT 47 #define BLOCK_SIZE (UL(1) << BLOCK_SHIFT) 48 #define BLOCK_MASK (~(BLOCK_SIZE-1)) 49 #endif 50 51 /***************************************************************/ 52 53 /* 54 * Memory types 55 */ 56 #define MT_DEVICE_NGNRNE 0 57 #define MT_DEVICE_NGNRE 1 58 #define MT_DEVICE_GRE 2 59 #define MT_NORMAL_NC 3 60 #define MT_NORMAL 4 61 62 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ 63 (0x04 << (MT_DEVICE_NGNRE * 8)) | \ 64 (0x0c << (MT_DEVICE_GRE * 8)) | \ 65 (0x44 << (MT_NORMAL_NC * 8)) | \ 66 (UL(0xff) << (MT_NORMAL * 8))) 67 68 /* 69 * Hardware page table definitions. 70 * 71 */ 72 73 #ifdef CONFIG_SYS_FULL_VA 74 /* 75 * Level 1 descriptor (PGD). 76 */ 77 78 #define PTL1_TYPE_MASK (3 << 0) 79 #define PTL1_TYPE_TABLE (3 << 0) 80 81 #define PTL1_TABLE_PXN (1UL << 59) 82 #define PTL1_TABLE_XN (1UL << 60) 83 #define PTL1_TABLE_AP (1UL << 61) 84 #define PTL1_TABLE_NS (1UL << 63) 85 86 87 /* 88 * Level 2 descriptor (PMD). 89 */ 90 91 #define PTL2_TYPE_MASK (3 << 0) 92 #define PTL2_TYPE_FAULT (0 << 0) 93 #define PTL2_TYPE_TABLE (3 << 0) 94 #define PTL2_TYPE_BLOCK (1 << 0) 95 96 /* 97 * Block 98 */ 99 #define PTL2_MEMTYPE(x) ((x) << 2) 100 #define PTL2_BLOCK_NON_SHARE (0 << 8) 101 #define PTL2_BLOCK_OUTER_SHARE (2 << 8) 102 #define PTL2_BLOCK_INNER_SHARE (3 << 8) 103 #define PTL2_BLOCK_AF (1 << 10) 104 #define PTL2_BLOCK_NG (1 << 11) 105 #define PTL2_BLOCK_PXN (UL(1) << 53) 106 #define PTL2_BLOCK_UXN (UL(1) << 54) 107 108 #else 109 /* 110 * Level 2 descriptor (PMD). 111 */ 112 #define PMD_TYPE_MASK (3 << 0) 113 #define PMD_TYPE_FAULT (0 << 0) 114 #define PMD_TYPE_TABLE (3 << 0) 115 #define PMD_TYPE_SECT (1 << 0) 116 117 /* 118 * Section 119 */ 120 #define PMD_SECT_NS (1 << 5) 121 #define PMD_SECT_NON_SHARE (0 << 8) 122 #define PMD_SECT_OUTER_SHARE (2 << 8) 123 #define PMD_SECT_INNER_SHARE (3 << 8) 124 #define PMD_SECT_AF (1 << 10) 125 #define PMD_SECT_NG (1 << 11) 126 #define PMD_SECT_PXN (UL(1) << 53) 127 #define PMD_SECT_UXN (UL(1) << 54) 128 129 #endif 130 131 /* 132 * AttrIndx[2:0] 133 */ 134 #define PMD_ATTRINDX(t) ((t) << 2) 135 #define PMD_ATTRINDX_MASK (7 << 2) 136 137 /* 138 * TCR flags. 139 */ 140 #define TCR_T0SZ(x) ((64 - (x)) << 0) 141 #define TCR_IRGN_NC (0 << 8) 142 #define TCR_IRGN_WBWA (1 << 8) 143 #define TCR_IRGN_WT (2 << 8) 144 #define TCR_IRGN_WBNWA (3 << 8) 145 #define TCR_IRGN_MASK (3 << 8) 146 #define TCR_ORGN_NC (0 << 10) 147 #define TCR_ORGN_WBWA (1 << 10) 148 #define TCR_ORGN_WT (2 << 10) 149 #define TCR_ORGN_WBNWA (3 << 10) 150 #define TCR_ORGN_MASK (3 << 10) 151 #define TCR_SHARED_NON (0 << 12) 152 #define TCR_SHARED_OUTER (2 << 12) 153 #define TCR_SHARED_INNER (3 << 12) 154 #define TCR_TG0_4K (0 << 14) 155 #define TCR_TG0_64K (1 << 14) 156 #define TCR_TG0_16K (2 << 14) 157 158 #ifndef CONFIG_SYS_FULL_VA 159 #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ 160 #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ 161 #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ 162 #else 163 #define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS 164 #define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS 165 #define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS 166 #endif 167 168 /* PTWs cacheable, inner/outer WBWA and inner shareable */ 169 #define TCR_FLAGS (TCR_TG0_64K | \ 170 TCR_SHARED_INNER | \ 171 TCR_ORGN_WBWA | \ 172 TCR_IRGN_WBWA | \ 173 TCR_T0SZ(VA_BITS)) 174 175 #define TCR_EL1_RSVD (1 << 31) 176 #define TCR_EL2_RSVD (1 << 31 | 1 << 23) 177 #define TCR_EL3_RSVD (1 << 31 | 1 << 23) 178 179 #ifndef __ASSEMBLY__ 180 #ifndef CONFIG_SYS_FULL_VA 181 182 void set_pgtable_section(u64 *page_table, u64 index, 183 u64 section, u64 memory_type, 184 u64 attribute); 185 void set_pgtable_table(u64 *page_table, u64 index, 186 u64 *table_addr); 187 188 #endif 189 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) 190 { 191 asm volatile("dsb sy"); 192 if (el == 1) { 193 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); 194 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); 195 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); 196 } else if (el == 2) { 197 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); 198 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); 199 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); 200 } else if (el == 3) { 201 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); 202 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); 203 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); 204 } else { 205 hang(); 206 } 207 asm volatile("isb"); 208 } 209 210 struct mm_region { 211 u64 base; 212 u64 size; 213 u64 attrs; 214 }; 215 #endif 216 217 #endif /* _ASM_ARMV8_MMU_H_ */ 218