xref: /openbmc/u-boot/arch/arm/include/asm/armv8/mmu.h (revision 224f7452)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2013
4  * David Feng <fenghua@phytium.com.cn>
5  */
6 
7 #ifndef _ASM_ARMV8_MMU_H_
8 #define _ASM_ARMV8_MMU_H_
9 
10 #include <linux/const.h>
11 
12 /*
13  * block/section address mask and size definitions.
14  */
15 
16 /* PAGE_SHIFT determines the page size */
17 #undef  PAGE_SIZE
18 #define PAGE_SHIFT		12
19 #define PAGE_SIZE		(1 << PAGE_SHIFT)
20 #define PAGE_MASK		(~(PAGE_SIZE - 1))
21 
22 /***************************************************************/
23 
24 /*
25  * Memory types
26  */
27 #define MT_DEVICE_NGNRNE	0
28 #define MT_DEVICE_NGNRE		1
29 #define MT_DEVICE_GRE		2
30 #define MT_NORMAL_NC		3
31 #define MT_NORMAL		4
32 
33 #define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE * 8)) |	\
34 				(0x04 << (MT_DEVICE_NGNRE * 8))   |	\
35 				(0x0c << (MT_DEVICE_GRE * 8))     |	\
36 				(0x44 << (MT_NORMAL_NC * 8))      |	\
37 				(UL(0xff) << (MT_NORMAL * 8)))
38 
39 /*
40  * Hardware page table definitions.
41  *
42  */
43 
44 #define PTE_TYPE_MASK		(3 << 0)
45 #define PTE_TYPE_FAULT		(0 << 0)
46 #define PTE_TYPE_TABLE		(3 << 0)
47 #define PTE_TYPE_PAGE		(3 << 0)
48 #define PTE_TYPE_BLOCK		(1 << 0)
49 #define PTE_TYPE_VALID		(1 << 0)
50 
51 #define PTE_TABLE_PXN		(1UL << 59)
52 #define PTE_TABLE_XN		(1UL << 60)
53 #define PTE_TABLE_AP		(1UL << 61)
54 #define PTE_TABLE_NS		(1UL << 63)
55 
56 /*
57  * Block
58  */
59 #define PTE_BLOCK_MEMTYPE(x)	((x) << 2)
60 #define PTE_BLOCK_NS            (1 << 5)
61 #define PTE_BLOCK_NON_SHARE	(0 << 8)
62 #define PTE_BLOCK_OUTER_SHARE	(2 << 8)
63 #define PTE_BLOCK_INNER_SHARE	(3 << 8)
64 #define PTE_BLOCK_AF		(1 << 10)
65 #define PTE_BLOCK_NG		(1 << 11)
66 #define PTE_BLOCK_PXN		(UL(1) << 53)
67 #define PTE_BLOCK_UXN		(UL(1) << 54)
68 
69 /*
70  * AttrIndx[2:0]
71  */
72 #define PMD_ATTRINDX(t)		((t) << 2)
73 #define PMD_ATTRINDX_MASK	(7 << 2)
74 #define PMD_ATTRMASK		(PTE_BLOCK_PXN		| \
75 				 PTE_BLOCK_UXN		| \
76 				 PMD_ATTRINDX_MASK	| \
77 				 PTE_TYPE_VALID)
78 
79 /*
80  * TCR flags.
81  */
82 #define TCR_T0SZ(x)		((64 - (x)) << 0)
83 #define TCR_IRGN_NC		(0 << 8)
84 #define TCR_IRGN_WBWA		(1 << 8)
85 #define TCR_IRGN_WT		(2 << 8)
86 #define TCR_IRGN_WBNWA		(3 << 8)
87 #define TCR_IRGN_MASK		(3 << 8)
88 #define TCR_ORGN_NC		(0 << 10)
89 #define TCR_ORGN_WBWA		(1 << 10)
90 #define TCR_ORGN_WT		(2 << 10)
91 #define TCR_ORGN_WBNWA		(3 << 10)
92 #define TCR_ORGN_MASK		(3 << 10)
93 #define TCR_SHARED_NON		(0 << 12)
94 #define TCR_SHARED_OUTER	(2 << 12)
95 #define TCR_SHARED_INNER	(3 << 12)
96 #define TCR_TG0_4K		(0 << 14)
97 #define TCR_TG0_64K		(1 << 14)
98 #define TCR_TG0_16K		(2 << 14)
99 #define TCR_EPD1_DISABLE	(1 << 23)
100 
101 #define TCR_EL1_RSVD		(1 << 31)
102 #define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
103 #define TCR_EL3_RSVD		(1 << 31 | 1 << 23)
104 
105 #ifndef __ASSEMBLY__
106 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
107 {
108 	asm volatile("dsb sy");
109 	if (el == 1) {
110 		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
111 		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
112 		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
113 	} else if (el == 2) {
114 		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
115 		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
116 		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
117 	} else if (el == 3) {
118 		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
119 		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
120 		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
121 	} else {
122 		hang();
123 	}
124 	asm volatile("isb");
125 }
126 
127 struct mm_region {
128 	u64 virt;
129 	u64 phys;
130 	u64 size;
131 	u64 attrs;
132 };
133 
134 extern struct mm_region *mem_map;
135 void setup_pgtables(void);
136 u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
137 #endif
138 
139 #endif /* _ASM_ARMV8_MMU_H_ */
140