1*f2ef2043SLokesh Vutla /* SPDX-License-Identifier: GPL-2.0+ */
2*f2ef2043SLokesh Vutla /*
3*f2ef2043SLokesh Vutla * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4*f2ef2043SLokesh Vutla * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5*f2ef2043SLokesh Vutla */
6*f2ef2043SLokesh Vutla
7*f2ef2043SLokesh Vutla #ifndef _ASM_ARMV7_MPU_H
8*f2ef2043SLokesh Vutla #define _ASM_ARMV7_MPU_H
9*f2ef2043SLokesh Vutla
10*f2ef2043SLokesh Vutla #ifdef CONFIG_CPU_V7M
11*f2ef2043SLokesh Vutla #define AP_SHIFT 24
12*f2ef2043SLokesh Vutla #define XN_SHIFT 28
13*f2ef2043SLokesh Vutla #define TEX_SHIFT 19
14*f2ef2043SLokesh Vutla #define S_SHIFT 18
15*f2ef2043SLokesh Vutla #define C_SHIFT 17
16*f2ef2043SLokesh Vutla #define B_SHIFT 16
17*f2ef2043SLokesh Vutla #else /* CONFIG_CPU_V7R */
18*f2ef2043SLokesh Vutla #define XN_SHIFT 12
19*f2ef2043SLokesh Vutla #define AP_SHIFT 8
20*f2ef2043SLokesh Vutla #define TEX_SHIFT 3
21*f2ef2043SLokesh Vutla #define S_SHIFT 2
22*f2ef2043SLokesh Vutla #define C_SHIFT 1
23*f2ef2043SLokesh Vutla #define B_SHIFT 0
24*f2ef2043SLokesh Vutla #endif /* CONFIG_CPU_V7R */
25*f2ef2043SLokesh Vutla
26*f2ef2043SLokesh Vutla #define CACHEABLE BIT(C_SHIFT)
27*f2ef2043SLokesh Vutla #define BUFFERABLE BIT(B_SHIFT)
28*f2ef2043SLokesh Vutla #define SHAREABLE BIT(S_SHIFT)
29*f2ef2043SLokesh Vutla #define REGION_SIZE_SHIFT 1
30*f2ef2043SLokesh Vutla #define ENABLE_REGION BIT(0)
31*f2ef2043SLokesh Vutla #define DISABLE_REGION 0
32*f2ef2043SLokesh Vutla
33*f2ef2043SLokesh Vutla enum region_number {
34*f2ef2043SLokesh Vutla REGION_0 = 0,
35*f2ef2043SLokesh Vutla REGION_1,
36*f2ef2043SLokesh Vutla REGION_2,
37*f2ef2043SLokesh Vutla REGION_3,
38*f2ef2043SLokesh Vutla REGION_4,
39*f2ef2043SLokesh Vutla REGION_5,
40*f2ef2043SLokesh Vutla REGION_6,
41*f2ef2043SLokesh Vutla REGION_7,
42*f2ef2043SLokesh Vutla };
43*f2ef2043SLokesh Vutla
44*f2ef2043SLokesh Vutla enum ap {
45*f2ef2043SLokesh Vutla NO_ACCESS = 0,
46*f2ef2043SLokesh Vutla PRIV_RW_USR_NO,
47*f2ef2043SLokesh Vutla PRIV_RW_USR_RO,
48*f2ef2043SLokesh Vutla PRIV_RW_USR_RW,
49*f2ef2043SLokesh Vutla UNPREDICTABLE,
50*f2ef2043SLokesh Vutla PRIV_RO_USR_NO,
51*f2ef2043SLokesh Vutla PRIV_RO_USR_RO,
52*f2ef2043SLokesh Vutla };
53*f2ef2043SLokesh Vutla
54*f2ef2043SLokesh Vutla enum mr_attr {
55*f2ef2043SLokesh Vutla STRONG_ORDER = 0,
56*f2ef2043SLokesh Vutla SHARED_WRITE_BUFFERED,
57*f2ef2043SLokesh Vutla O_I_WT_NO_WR_ALLOC,
58*f2ef2043SLokesh Vutla O_I_WB_NO_WR_ALLOC,
59*f2ef2043SLokesh Vutla O_I_NON_CACHEABLE,
60*f2ef2043SLokesh Vutla O_I_WB_RD_WR_ALLOC,
61*f2ef2043SLokesh Vutla DEVICE_NON_SHARED,
62*f2ef2043SLokesh Vutla };
63*f2ef2043SLokesh Vutla enum size {
64*f2ef2043SLokesh Vutla REGION_8MB = 22,
65*f2ef2043SLokesh Vutla REGION_16MB,
66*f2ef2043SLokesh Vutla REGION_32MB,
67*f2ef2043SLokesh Vutla REGION_64MB,
68*f2ef2043SLokesh Vutla REGION_128MB,
69*f2ef2043SLokesh Vutla REGION_256MB,
70*f2ef2043SLokesh Vutla REGION_512MB,
71*f2ef2043SLokesh Vutla REGION_1GB,
72*f2ef2043SLokesh Vutla REGION_2GB,
73*f2ef2043SLokesh Vutla REGION_4GB,
74*f2ef2043SLokesh Vutla };
75*f2ef2043SLokesh Vutla
76*f2ef2043SLokesh Vutla enum xn {
77*f2ef2043SLokesh Vutla XN_DIS = 0,
78*f2ef2043SLokesh Vutla XN_EN,
79*f2ef2043SLokesh Vutla };
80*f2ef2043SLokesh Vutla
81*f2ef2043SLokesh Vutla struct mpu_region_config {
82*f2ef2043SLokesh Vutla uint32_t start_addr;
83*f2ef2043SLokesh Vutla enum region_number region_no;
84*f2ef2043SLokesh Vutla enum xn xn;
85*f2ef2043SLokesh Vutla enum ap ap;
86*f2ef2043SLokesh Vutla enum mr_attr mr_attr;
87*f2ef2043SLokesh Vutla enum size reg_size;
88*f2ef2043SLokesh Vutla };
89*f2ef2043SLokesh Vutla
90*f2ef2043SLokesh Vutla void disable_mpu(void);
91*f2ef2043SLokesh Vutla void enable_mpu(void);
92*f2ef2043SLokesh Vutla int mpu_enabled(void);
93*f2ef2043SLokesh Vutla void mpu_config(struct mpu_region_config *reg_config);
94*f2ef2043SLokesh Vutla void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns);
95*f2ef2043SLokesh Vutla
get_attr_encoding(u32 mr_attr)96*f2ef2043SLokesh Vutla static inline u32 get_attr_encoding(u32 mr_attr)
97*f2ef2043SLokesh Vutla {
98*f2ef2043SLokesh Vutla u32 attr;
99*f2ef2043SLokesh Vutla
100*f2ef2043SLokesh Vutla switch (mr_attr) {
101*f2ef2043SLokesh Vutla case STRONG_ORDER:
102*f2ef2043SLokesh Vutla attr = SHAREABLE;
103*f2ef2043SLokesh Vutla break;
104*f2ef2043SLokesh Vutla case SHARED_WRITE_BUFFERED:
105*f2ef2043SLokesh Vutla attr = BUFFERABLE;
106*f2ef2043SLokesh Vutla break;
107*f2ef2043SLokesh Vutla case O_I_WT_NO_WR_ALLOC:
108*f2ef2043SLokesh Vutla attr = CACHEABLE;
109*f2ef2043SLokesh Vutla break;
110*f2ef2043SLokesh Vutla case O_I_WB_NO_WR_ALLOC:
111*f2ef2043SLokesh Vutla attr = CACHEABLE | BUFFERABLE;
112*f2ef2043SLokesh Vutla break;
113*f2ef2043SLokesh Vutla case O_I_NON_CACHEABLE:
114*f2ef2043SLokesh Vutla attr = 1 << TEX_SHIFT;
115*f2ef2043SLokesh Vutla break;
116*f2ef2043SLokesh Vutla case O_I_WB_RD_WR_ALLOC:
117*f2ef2043SLokesh Vutla attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
118*f2ef2043SLokesh Vutla break;
119*f2ef2043SLokesh Vutla case DEVICE_NON_SHARED:
120*f2ef2043SLokesh Vutla attr = (2 << TEX_SHIFT) | BUFFERABLE;
121*f2ef2043SLokesh Vutla break;
122*f2ef2043SLokesh Vutla default:
123*f2ef2043SLokesh Vutla attr = 0; /* strongly ordered */
124*f2ef2043SLokesh Vutla break;
125*f2ef2043SLokesh Vutla };
126*f2ef2043SLokesh Vutla
127*f2ef2043SLokesh Vutla return attr;
128*f2ef2043SLokesh Vutla }
129*f2ef2043SLokesh Vutla
130*f2ef2043SLokesh Vutla #endif /* _ASM_ARMV7_MPU_H */
131