1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * Aneesh V <aneesh@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 #ifndef ARMV7_H 25 #define ARMV7_H 26 #include <linux/types.h> 27 28 /* CCSIDR */ 29 #define CCSIDR_LINE_SIZE_OFFSET 0 30 #define CCSIDR_LINE_SIZE_MASK 0x7 31 #define CCSIDR_ASSOCIATIVITY_OFFSET 3 32 #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) 33 #define CCSIDR_NUM_SETS_OFFSET 13 34 #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) 35 36 /* 37 * Values for InD field in CSSELR 38 * Selects the type of cache 39 */ 40 #define ARMV7_CSSELR_IND_DATA_UNIFIED 0 41 #define ARMV7_CSSELR_IND_INSTRUCTION 1 42 43 /* Values for Ctype fields in CLIDR */ 44 #define ARMV7_CLIDR_CTYPE_NO_CACHE 0 45 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 46 #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 47 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 48 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 49 50 /* 51 * CP15 Barrier instructions 52 * Please note that we have separate barrier instructions in ARMv7 53 * However, we use the CP15 based instructtions because we use 54 * -march=armv5 in U-Boot 55 */ 56 #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) 57 #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) 58 #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) 59 60 void v7_outer_cache_enable(void); 61 void v7_outer_cache_disable(void); 62 void v7_outer_cache_flush_all(void); 63 void v7_outer_cache_inval_all(void); 64 void v7_outer_cache_flush_range(u32 start, u32 end); 65 void v7_outer_cache_inval_range(u32 start, u32 end); 66 67 #endif 68