1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ 21 #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ 22 23 #ifndef __ASSEMBLY__ 24 25 /* Clock Controller Module (CCM) */ 26 struct ccm_reg { 27 u32 ccr; 28 u32 csr; 29 u32 ccsr; 30 u32 cacrr; 31 u32 cscmr1; 32 u32 cscdr1; 33 u32 cscdr2; 34 u32 cscdr3; 35 u32 cscmr2; 36 u32 cscdr4; 37 u32 ctor; 38 u32 clpcr; 39 u32 cisr; 40 u32 cimr; 41 u32 ccosr; 42 u32 cgpr; 43 u32 ccgr0; 44 u32 ccgr1; 45 u32 ccgr2; 46 u32 ccgr3; 47 u32 ccgr4; 48 u32 ccgr5; 49 u32 ccgr6; 50 u32 ccgr7; 51 u32 ccgr8; 52 u32 ccgr9; 53 u32 ccgr10; 54 u32 ccgr11; 55 u32 cmeor0; 56 u32 cmeor1; 57 u32 cmeor2; 58 u32 cmeor3; 59 u32 cmeor4; 60 u32 cmeor5; 61 u32 cppdsr; 62 u32 ccowr; 63 u32 ccpgr0; 64 u32 ccpgr1; 65 u32 ccpgr2; 66 u32 ccpgr3; 67 }; 68 69 /* Analog components control digital interface (ANADIG) */ 70 struct anadig_reg { 71 u32 pll3_ctrl; 72 u32 resv0[3]; 73 u32 pll7_ctrl; 74 u32 resv1[3]; 75 u32 pll2_ctrl; 76 u32 resv2[3]; 77 u32 pll2_ss; 78 u32 resv3[3]; 79 u32 pll2_num; 80 u32 resv4[3]; 81 u32 pll2_denom; 82 u32 resv5[3]; 83 u32 pll4_ctrl; 84 u32 resv6[3]; 85 u32 pll4_num; 86 u32 resv7[3]; 87 u32 pll4_denom; 88 u32 pll6_ctrl; 89 u32 resv8[3]; 90 u32 pll6_num; 91 u32 resv9[3]; 92 u32 pll6_denom; 93 u32 resv10[3]; 94 u32 pll5_ctrl; 95 u32 resv11[3]; 96 u32 pll3_pfd; 97 u32 resv12[3]; 98 u32 pll2_pfd; 99 u32 resv13[3]; 100 u32 reg_1p1; 101 u32 resv14[3]; 102 u32 reg_3p0; 103 u32 resv15[3]; 104 u32 reg_2p5; 105 u32 resv16[7]; 106 u32 ana_misc0; 107 u32 resv17[3]; 108 u32 ana_misc1; 109 u32 resv18[63]; 110 u32 anadig_digprog; 111 u32 resv19[3]; 112 u32 pll1_ctrl; 113 u32 resv20[3]; 114 u32 pll1_ss; 115 u32 resv21[3]; 116 u32 pll1_num; 117 u32 resv22[3]; 118 u32 pll1_denom; 119 u32 resv23[3]; 120 u32 pll1_pdf; 121 u32 resv24[3]; 122 u32 pll_lock; 123 }; 124 #endif 125 126 #define CCM_CCR_FIRC_EN (1 << 16) 127 #define CCM_CCR_OSCNT_MASK 0xff 128 #define CCM_CCR_OSCNT(v) ((v) & 0xff) 129 130 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 131 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) 132 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) 133 134 #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 135 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) 136 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) 137 138 #define CCM_CCSR_PLL2_PFD4_EN (1 << 15) 139 #define CCM_CCSR_PLL2_PFD3_EN (1 << 14) 140 #define CCM_CCSR_PLL2_PFD2_EN (1 << 13) 141 #define CCM_CCSR_PLL2_PFD1_EN (1 << 12) 142 #define CCM_CCSR_PLL1_PFD4_EN (1 << 11) 143 #define CCM_CCSR_PLL1_PFD3_EN (1 << 10) 144 #define CCM_CCSR_PLL1_PFD2_EN (1 << 9) 145 #define CCM_CCSR_PLL1_PFD1_EN (1 << 8) 146 147 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) 148 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) 149 150 #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 151 #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 152 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) 153 154 #define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 155 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) 156 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) 157 #define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 158 #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) 159 #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) 160 #define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 161 #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 162 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) 163 164 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 165 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) 166 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) 167 168 #define CCM_CSCDR1_RMII_CLK_EN (1 << 24) 169 170 #define CCM_CSCDR2_ESDHC1_EN (1 << 29) 171 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 172 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) 173 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) 174 175 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 176 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) 177 #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) 178 179 #define CCM_REG_CTRL_MASK 0xffffffff 180 #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) 181 #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) 182 #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) 183 #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) 184 #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) 185 #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) 186 #define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) 187 #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) 188 #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) 189 #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 190 #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) 191 #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) 192 #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) 193 #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) 194 #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) 195 #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) 196 #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 197 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) 198 199 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) 200 #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) 201 #define ANADIG_PLL2_CTRL_DIV_SELECT 1 202 #define ANADIG_PLL1_CTRL_ENABLE (1 << 13) 203 #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) 204 #define ANADIG_PLL1_CTRL_DIV_SELECT 1 205 206 #define FASE_CLK_FREQ 24000000 207 #define SLOW_CLK_FREQ 32000 208 #define PLL1_PFD1_FREQ 500000000 209 #define PLL1_PFD2_FREQ 452000000 210 #define PLL1_PFD3_FREQ 396000000 211 #define PLL1_PFD4_FREQ 528000000 212 #define PLL1_MAIN_FREQ 528000000 213 #define PLL2_PFD1_FREQ 500000000 214 #define PLL2_PFD2_FREQ 396000000 215 #define PLL2_PFD3_FREQ 339000000 216 #define PLL2_PFD4_FREQ 413000000 217 #define PLL2_MAIN_FREQ 528000000 218 #define PLL3_MAIN_FREQ 480000000 219 #define PLL3_PFD3_FREQ 298000000 220 #define PLL5_MAIN_FREQ 500000000 221 222 #define ENET_EXTERNAL_CLK 50000000 223 #define AUDIO_EXTERNAL_CLK 24576000 224 225 #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ 226