1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ 8 #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ 9 10 #ifndef __ASSEMBLY__ 11 12 /* Clock Controller Module (CCM) */ 13 struct ccm_reg { 14 u32 ccr; 15 u32 csr; 16 u32 ccsr; 17 u32 cacrr; 18 u32 cscmr1; 19 u32 cscdr1; 20 u32 cscdr2; 21 u32 cscdr3; 22 u32 cscmr2; 23 u32 cscdr4; 24 u32 ctor; 25 u32 clpcr; 26 u32 cisr; 27 u32 cimr; 28 u32 ccosr; 29 u32 cgpr; 30 u32 ccgr0; 31 u32 ccgr1; 32 u32 ccgr2; 33 u32 ccgr3; 34 u32 ccgr4; 35 u32 ccgr5; 36 u32 ccgr6; 37 u32 ccgr7; 38 u32 ccgr8; 39 u32 ccgr9; 40 u32 ccgr10; 41 u32 ccgr11; 42 u32 cmeor0; 43 u32 cmeor1; 44 u32 cmeor2; 45 u32 cmeor3; 46 u32 cmeor4; 47 u32 cmeor5; 48 u32 cppdsr; 49 u32 ccowr; 50 u32 ccpgr0; 51 u32 ccpgr1; 52 u32 ccpgr2; 53 u32 ccpgr3; 54 }; 55 56 /* Analog components control digital interface (ANADIG) */ 57 struct anadig_reg { 58 u32 reserved_0x000[4]; 59 u32 pll3_ctrl; 60 u32 reserved_0x014[3]; 61 u32 pll7_ctrl; 62 u32 reserved_0x024[3]; 63 u32 pll2_ctrl; 64 u32 reserved_0x034[3]; 65 u32 pll2_ss; 66 u32 reserved_0x044[3]; 67 u32 pll2_num; 68 u32 reserved_0x054[3]; 69 u32 pll2_denom; 70 u32 reserved_0x064[3]; 71 u32 pll4_ctrl; 72 u32 reserved_0x074[3]; 73 u32 pll4_num; 74 u32 reserved_0x084[3]; 75 u32 pll4_denom; 76 u32 reserved_0x094[3]; 77 u32 pll6_ctrl; 78 u32 reserved_0x0A4[3]; 79 u32 pll6_num; 80 u32 reserved_0x0B4[3]; 81 u32 pll6_denom; 82 u32 reserved_0x0C4[7]; 83 u32 pll5_ctrl; 84 u32 reserved_0x0E4[3]; 85 u32 pll3_pfd; 86 u32 reserved_0x0F4[3]; 87 u32 pll2_pfd; 88 u32 reserved_0x104[3]; 89 u32 reg_1p1; 90 u32 reserved_0x114[3]; 91 u32 reg_3p0; 92 u32 reserved_0x124[3]; 93 u32 reg_2p5; 94 u32 reserved_0x134[7]; 95 u32 ana_misc0; 96 u32 reserved_0x154[3]; 97 u32 ana_misc1; 98 u32 reserved_0x164[63]; 99 u32 anadig_digprog; 100 u32 reserved_0x264[3]; 101 u32 pll1_ctrl; 102 u32 reserved_0x274[3]; 103 u32 pll1_ss; 104 u32 reserved_0x284[3]; 105 u32 pll1_num; 106 u32 reserved_0x294[3]; 107 u32 pll1_denom; 108 u32 reserved_0x2A4[3]; 109 u32 pll1_pdf; 110 u32 reserved_0x2B4[3]; 111 u32 pll_lock; 112 }; 113 #endif 114 115 #define CCM_CCR_FIRC_EN (1 << 16) 116 #define CCM_CCR_OSCNT_MASK 0xff 117 #define CCM_CCR_OSCNT(v) ((v) & 0xff) 118 119 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 120 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) 121 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) 122 123 #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 124 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) 125 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) 126 127 #define CCM_CCSR_PLL2_PFD4_EN (1 << 15) 128 #define CCM_CCSR_PLL2_PFD3_EN (1 << 14) 129 #define CCM_CCSR_PLL2_PFD2_EN (1 << 13) 130 #define CCM_CCSR_PLL2_PFD1_EN (1 << 12) 131 #define CCM_CCSR_PLL1_PFD4_EN (1 << 11) 132 #define CCM_CCSR_PLL1_PFD3_EN (1 << 10) 133 #define CCM_CCSR_PLL1_PFD2_EN (1 << 9) 134 #define CCM_CCSR_PLL1_PFD1_EN (1 << 8) 135 136 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) 137 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) 138 139 #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 140 #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 141 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) 142 143 #define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 144 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) 145 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) 146 #define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 147 #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) 148 #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) 149 #define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 150 #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 151 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) 152 153 #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 154 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) 155 #define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) 156 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 157 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) 158 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) 159 160 #define CCM_CSCDR1_RMII_CLK_EN (1 << 24) 161 162 #define CCM_CSCDR2_ESDHC1_EN (1 << 29) 163 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 164 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) 165 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) 166 167 #define CCM_CSCDR3_QSPI0_EN (1 << 4) 168 #define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) 169 #define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) 170 #define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) 171 172 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 173 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) 174 #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) 175 176 #define CCM_REG_CTRL_MASK 0xffffffff 177 #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) 178 #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) 179 #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) 180 #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) 181 #define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) 182 #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) 183 #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) 184 #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) 185 #define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) 186 #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) 187 #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) 188 #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 189 #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) 190 #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) 191 #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) 192 #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) 193 #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) 194 #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) 195 #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) 196 #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 197 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) 198 199 #define ANADIG_PLL5_CTRL_BYPASS (1 << 16) 200 #define ANADIG_PLL5_CTRL_ENABLE (1 << 13) 201 #define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) 202 #define ANADIG_PLL5_CTRL_DIV_SELECT 1 203 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) 204 #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) 205 #define ANADIG_PLL2_CTRL_DIV_SELECT 1 206 #define ANADIG_PLL1_CTRL_ENABLE (1 << 13) 207 #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) 208 #define ANADIG_PLL1_CTRL_DIV_SELECT 1 209 210 #define FASE_CLK_FREQ 24000000 211 #define SLOW_CLK_FREQ 32000 212 #define PLL1_PFD1_FREQ 500000000 213 #define PLL1_PFD2_FREQ 452000000 214 #define PLL1_PFD3_FREQ 396000000 215 #define PLL1_PFD4_FREQ 528000000 216 #define PLL1_MAIN_FREQ 528000000 217 #define PLL2_PFD1_FREQ 500000000 218 #define PLL2_PFD2_FREQ 396000000 219 #define PLL2_PFD3_FREQ 339000000 220 #define PLL2_PFD4_FREQ 413000000 221 #define PLL2_MAIN_FREQ 528000000 222 #define PLL3_MAIN_FREQ 480000000 223 #define PLL3_PFD3_FREQ 298000000 224 #define PLL5_MAIN_FREQ 500000000 225 226 #define ENET_EXTERNAL_CLK 50000000 227 #define AUDIO_EXTERNAL_CLK 24576000 228 229 #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ 230