1 /*
2  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #ifndef _TEGRA30_PINMUX_H_
18 #define _TEGRA30_PINMUX_H_
19 
20 /*
21  * Pin groups which we adjust. There are three basic attributes of each pin
22  * group which use this enum:
23  *
24  *	- function
25  *	- pullup / pulldown
26  *	- tristate or normal
27  */
28 enum pmux_pingrp {
29 	PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
30 	PINGRP_ULPI_DATA1,
31 	PINGRP_ULPI_DATA2,
32 	PINGRP_ULPI_DATA3,
33 	PINGRP_ULPI_DATA4,
34 	PINGRP_ULPI_DATA5,
35 	PINGRP_ULPI_DATA6,
36 	PINGRP_ULPI_DATA7,
37 	PINGRP_ULPI_CLK,
38 	PINGRP_ULPI_DIR,
39 	PINGRP_ULPI_NXT,
40 	PINGRP_ULPI_STP,
41 	PINGRP_DAP3_FS,
42 	PINGRP_DAP3_DIN,
43 	PINGRP_DAP3_DOUT,
44 	PINGRP_DAP3_SCLK,
45 	PINGRP_GPIO_PV0,
46 	PINGRP_GPIO_PV1,
47 	PINGRP_SDMMC1_CLK,
48 	PINGRP_SDMMC1_CMD,
49 	PINGRP_SDMMC1_DAT3,
50 	PINGRP_SDMMC1_DAT2,
51 	PINGRP_SDMMC1_DAT1,
52 	PINGRP_SDMMC1_DAT0,
53 	PINGRP_GPIO_PV2,
54 	PINGRP_GPIO_PV3,
55 	PINGRP_CLK2_OUT,
56 	PINGRP_CLK2_REQ,
57 	PINGRP_LCD_PWR1,
58 	PINGRP_LCD_PWR2,
59 	PINGRP_LCD_SDIN,
60 	PINGRP_LCD_SDOUT,
61 	PINGRP_LCD_WR_N,
62 	PINGRP_LCD_CS0_N,
63 	PINGRP_LCD_DC0,
64 	PINGRP_LCD_SCK,
65 	PINGRP_LCD_PWR0,
66 	PINGRP_LCD_PCLK,
67 	PINGRP_LCD_DE,
68 	PINGRP_LCD_HSYNC,
69 	PINGRP_LCD_VSYNC,
70 	PINGRP_LCD_D0,
71 	PINGRP_LCD_D1,
72 	PINGRP_LCD_D2,
73 	PINGRP_LCD_D3,
74 	PINGRP_LCD_D4,
75 	PINGRP_LCD_D5,
76 	PINGRP_LCD_D6,
77 	PINGRP_LCD_D7,
78 	PINGRP_LCD_D8,
79 	PINGRP_LCD_D9,
80 	PINGRP_LCD_D10,
81 	PINGRP_LCD_D11,
82 	PINGRP_LCD_D12,
83 	PINGRP_LCD_D13,
84 	PINGRP_LCD_D14,
85 	PINGRP_LCD_D15,
86 	PINGRP_LCD_D16,
87 	PINGRP_LCD_D17,
88 	PINGRP_LCD_D18,
89 	PINGRP_LCD_D19,
90 	PINGRP_LCD_D20,
91 	PINGRP_LCD_D21,
92 	PINGRP_LCD_D22,
93 	PINGRP_LCD_D23,
94 	PINGRP_LCD_CS1_N,
95 	PINGRP_LCD_M1,
96 	PINGRP_LCD_DC1,
97 	PINGRP_HDMI_INT,
98 	PINGRP_DDC_SCL,
99 	PINGRP_DDC_SDA,
100 	PINGRP_CRT_HSYNC,
101 	PINGRP_CRT_VSYNC,
102 	PINGRP_VI_D0,
103 	PINGRP_VI_D1,
104 	PINGRP_VI_D2,
105 	PINGRP_VI_D3,
106 	PINGRP_VI_D4,
107 	PINGRP_VI_D5,
108 	PINGRP_VI_D6,
109 	PINGRP_VI_D7,
110 	PINGRP_VI_D8,
111 	PINGRP_VI_D9,
112 	PINGRP_VI_D10,
113 	PINGRP_VI_D11,
114 	PINGRP_VI_PCLK,
115 	PINGRP_VI_MCLK,
116 	PINGRP_VI_VSYNC,
117 	PINGRP_VI_HSYNC,
118 	PINGRP_UART2_RXD,
119 	PINGRP_UART2_TXD,
120 	PINGRP_UART2_RTS_N,
121 	PINGRP_UART2_CTS_N,
122 	PINGRP_UART3_TXD,
123 	PINGRP_UART3_RXD,
124 	PINGRP_UART3_CTS_N,
125 	PINGRP_UART3_RTS_N,
126 	PINGRP_GPIO_PU0,
127 	PINGRP_GPIO_PU1,
128 	PINGRP_GPIO_PU2,
129 	PINGRP_GPIO_PU3,
130 	PINGRP_GPIO_PU4,
131 	PINGRP_GPIO_PU5,
132 	PINGRP_GPIO_PU6,
133 	PINGRP_GEN1_I2C_SDA,
134 	PINGRP_GEN1_I2C_SCL,
135 	PINGRP_DAP4_FS,
136 	PINGRP_DAP4_DIN,
137 	PINGRP_DAP4_DOUT,
138 	PINGRP_DAP4_SCLK,
139 	PINGRP_CLK3_OUT,
140 	PINGRP_CLK3_REQ,
141 	PINGRP_GMI_WP_N,
142 	PINGRP_GMI_IORDY,
143 	PINGRP_GMI_WAIT,
144 	PINGRP_GMI_ADV_N,
145 	PINGRP_GMI_CLK,
146 	PINGRP_GMI_CS0_N,
147 	PINGRP_GMI_CS1_N,
148 	PINGRP_GMI_CS2_N,
149 	PINGRP_GMI_CS3_N,
150 	PINGRP_GMI_CS4_N,
151 	PINGRP_GMI_CS6_N,
152 	PINGRP_GMI_CS7_N,
153 	PINGRP_GMI_AD0,
154 	PINGRP_GMI_AD1,
155 	PINGRP_GMI_AD2,
156 	PINGRP_GMI_AD3,
157 	PINGRP_GMI_AD4,
158 	PINGRP_GMI_AD5,
159 	PINGRP_GMI_AD6,
160 	PINGRP_GMI_AD7,
161 	PINGRP_GMI_AD8,
162 	PINGRP_GMI_AD9,
163 	PINGRP_GMI_AD10,
164 	PINGRP_GMI_AD11,
165 	PINGRP_GMI_AD12,
166 	PINGRP_GMI_AD13,
167 	PINGRP_GMI_AD14,
168 	PINGRP_GMI_AD15,
169 	PINGRP_GMI_A16,
170 	PINGRP_GMI_A17,
171 	PINGRP_GMI_A18,
172 	PINGRP_GMI_A19,
173 	PINGRP_GMI_WR_N,
174 	PINGRP_GMI_OE_N,
175 	PINGRP_GMI_DQS,
176 	PINGRP_GMI_RST_N,
177 	PINGRP_GEN2_I2C_SCL,
178 	PINGRP_GEN2_I2C_SDA,
179 	PINGRP_SDMMC4_CLK,
180 	PINGRP_SDMMC4_CMD,
181 	PINGRP_SDMMC4_DAT0,
182 	PINGRP_SDMMC4_DAT1,
183 	PINGRP_SDMMC4_DAT2,
184 	PINGRP_SDMMC4_DAT3,
185 	PINGRP_SDMMC4_DAT4,
186 	PINGRP_SDMMC4_DAT5,
187 	PINGRP_SDMMC4_DAT6,
188 	PINGRP_SDMMC4_DAT7,
189 	PINGRP_SDMMC4_RST_N,
190 	PINGRP_CAM_MCLK,
191 	PINGRP_GPIO_PCC1,
192 	PINGRP_GPIO_PBB0,
193 	PINGRP_CAM_I2C_SCL,
194 	PINGRP_CAM_I2C_SDA,
195 	PINGRP_GPIO_PBB3,
196 	PINGRP_GPIO_PBB4,
197 	PINGRP_GPIO_PBB5,
198 	PINGRP_GPIO_PBB6,
199 	PINGRP_GPIO_PBB7,
200 	PINGRP_GPIO_PCC2,
201 	PINGRP_JTAG_RTCK,
202 	PINGRP_PWR_I2C_SCL,
203 	PINGRP_PWR_I2C_SDA,
204 	PINGRP_KB_ROW0,
205 	PINGRP_KB_ROW1,
206 	PINGRP_KB_ROW2,
207 	PINGRP_KB_ROW3,
208 	PINGRP_KB_ROW4,
209 	PINGRP_KB_ROW5,
210 	PINGRP_KB_ROW6,
211 	PINGRP_KB_ROW7,
212 	PINGRP_KB_ROW8,
213 	PINGRP_KB_ROW9,
214 	PINGRP_KB_ROW10,
215 	PINGRP_KB_ROW11,
216 	PINGRP_KB_ROW12,
217 	PINGRP_KB_ROW13,
218 	PINGRP_KB_ROW14,
219 	PINGRP_KB_ROW15,
220 	PINGRP_KB_COL0,
221 	PINGRP_KB_COL1,
222 	PINGRP_KB_COL2,
223 	PINGRP_KB_COL3,
224 	PINGRP_KB_COL4,
225 	PINGRP_KB_COL5,
226 	PINGRP_KB_COL6,
227 	PINGRP_KB_COL7,
228 	PINGRP_CLK_32K_OUT,
229 	PINGRP_SYS_CLK_REQ,
230 	PINGRP_CORE_PWR_REQ,
231 	PINGRP_CPU_PWR_REQ,
232 	PINGRP_PWR_INT_N,
233 	PINGRP_CLK_32K_IN,
234 	PINGRP_OWR,
235 	PINGRP_DAP1_FS,
236 	PINGRP_DAP1_DIN,
237 	PINGRP_DAP1_DOUT,
238 	PINGRP_DAP1_SCLK,
239 	PINGRP_CLK1_REQ,
240 	PINGRP_CLK1_OUT,
241 	PINGRP_SPDIF_IN,
242 	PINGRP_SPDIF_OUT,
243 	PINGRP_DAP2_FS,
244 	PINGRP_DAP2_DIN,
245 	PINGRP_DAP2_DOUT,
246 	PINGRP_DAP2_SCLK,
247 	PINGRP_SPI2_MOSI,
248 	PINGRP_SPI2_MISO,
249 	PINGRP_SPI2_CS0_N,
250 	PINGRP_SPI2_SCK,
251 	PINGRP_SPI1_MOSI,
252 	PINGRP_SPI1_SCK,
253 	PINGRP_SPI1_CS0_N,
254 	PINGRP_SPI1_MISO,
255 	PINGRP_SPI2_CS1_N,
256 	PINGRP_SPI2_CS2_N,
257 	PINGRP_SDMMC3_CLK,
258 	PINGRP_SDMMC3_CMD,
259 	PINGRP_SDMMC3_DAT0,
260 	PINGRP_SDMMC3_DAT1,
261 	PINGRP_SDMMC3_DAT2,
262 	PINGRP_SDMMC3_DAT3,
263 	PINGRP_SDMMC3_DAT4,
264 	PINGRP_SDMMC3_DAT5,
265 	PINGRP_SDMMC3_DAT6,
266 	PINGRP_SDMMC3_DAT7,
267 	PINGRP_PEX_L0_PRSNT_N,
268 	PINGRP_PEX_L0_RST_N,
269 	PINGRP_PEX_L0_CLKREQ_N,
270 	PINGRP_PEX_WAKE_N,
271 	PINGRP_PEX_L1_PRSNT_N,
272 	PINGRP_PEX_L1_RST_N,
273 	PINGRP_PEX_L1_CLKREQ_N,
274 	PINGRP_PEX_L2_PRSNT_N,
275 	PINGRP_PEX_L2_RST_N,
276 	PINGRP_PEX_L2_CLKREQ_N,
277 	PINGRP_HDMI_CEC,	/* offset 0x33e0 */
278 	PINGRP_COUNT,
279 };
280 
281 enum pdrive_pingrp {
282 	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
283 	PDRIVE_PINGROUP_AO2,
284 	PDRIVE_PINGROUP_AT1,
285 	PDRIVE_PINGROUP_AT2,
286 	PDRIVE_PINGROUP_AT3,
287 	PDRIVE_PINGROUP_AT4,
288 	PDRIVE_PINGROUP_AT5,
289 	PDRIVE_PINGROUP_CDEV1,
290 	PDRIVE_PINGROUP_CDEV2,
291 	PDRIVE_PINGROUP_CSUS,
292 	PDRIVE_PINGROUP_DAP1,
293 	PDRIVE_PINGROUP_DAP2,
294 	PDRIVE_PINGROUP_DAP3,
295 	PDRIVE_PINGROUP_DAP4,
296 	PDRIVE_PINGROUP_DBG,
297 	PDRIVE_PINGROUP_LCD1,
298 	PDRIVE_PINGROUP_LCD2,
299 	PDRIVE_PINGROUP_SDIO2,
300 	PDRIVE_PINGROUP_SDIO3,
301 	PDRIVE_PINGROUP_SPI,
302 	PDRIVE_PINGROUP_UAA,
303 	PDRIVE_PINGROUP_UAB,
304 	PDRIVE_PINGROUP_UART2,
305 	PDRIVE_PINGROUP_UART3,
306 	PDRIVE_PINGROUP_VI1 = 24,	/* offset 0x8c8 */
307 	PDRIVE_PINGROUP_SDIO1 = 33,	/* offset 0x8ec */
308 	PDRIVE_PINGROUP_CRT = 36,	/* offset 0x8f8 */
309 	PDRIVE_PINGROUP_DDC,
310 	PDRIVE_PINGROUP_GMA,
311 	PDRIVE_PINGROUP_GMB,
312 	PDRIVE_PINGROUP_GMC,
313 	PDRIVE_PINGROUP_GMD,
314 	PDRIVE_PINGROUP_GME,
315 	PDRIVE_PINGROUP_GMF,
316 	PDRIVE_PINGROUP_GMG,
317 	PDRIVE_PINGROUP_GMH,
318 	PDRIVE_PINGROUP_OWR,
319 	PDRIVE_PINGROUP_UAD,
320 	PDRIVE_PINGROUP_GPV,
321 	PDRIVE_PINGROUP_DEV3 = 49,	/* offset 0x92c */
322 	PDRIVE_PINGROUP_CEC = 52,	/* offset 0x938 */
323 	PDRIVE_PINGROUP_COUNT,
324 };
325 
326 /*
327  * Functions which can be assigned to each of the pin groups. The values here
328  * bear no relation to the values programmed into pinmux registers and are
329  * purely a convenience. The translation is done through a table search.
330  */
331 enum pmux_func {
332 	PMUX_FUNC_AHB_CLK,
333 	PMUX_FUNC_APB_CLK,
334 	PMUX_FUNC_AUDIO_SYNC,
335 	PMUX_FUNC_CRT,
336 	PMUX_FUNC_DAP1,
337 	PMUX_FUNC_DAP2,
338 	PMUX_FUNC_DAP3,
339 	PMUX_FUNC_DAP4,
340 	PMUX_FUNC_DAP5,
341 	PMUX_FUNC_DISPA,
342 	PMUX_FUNC_DISPB,
343 	PMUX_FUNC_EMC_TEST0_DLL,
344 	PMUX_FUNC_EMC_TEST1_DLL,
345 	PMUX_FUNC_GMI,
346 	PMUX_FUNC_GMI_INT,
347 	PMUX_FUNC_HDMI,
348 	PMUX_FUNC_I2C1,
349 	PMUX_FUNC_I2C2,
350 	PMUX_FUNC_I2C3,
351 	PMUX_FUNC_IDE,
352 	PMUX_FUNC_KBC,
353 	PMUX_FUNC_MIO,
354 	PMUX_FUNC_MIPI_HS,
355 	PMUX_FUNC_NAND,
356 	PMUX_FUNC_OSC,
357 	PMUX_FUNC_OWR,
358 	PMUX_FUNC_PCIE,
359 	PMUX_FUNC_PLLA_OUT,
360 	PMUX_FUNC_PLLC_OUT1,
361 	PMUX_FUNC_PLLM_OUT1,
362 	PMUX_FUNC_PLLP_OUT2,
363 	PMUX_FUNC_PLLP_OUT3,
364 	PMUX_FUNC_PLLP_OUT4,
365 	PMUX_FUNC_PWM,
366 	PMUX_FUNC_PWR_INTR,
367 	PMUX_FUNC_PWR_ON,
368 	PMUX_FUNC_RTCK,
369 	PMUX_FUNC_SDMMC1,
370 	PMUX_FUNC_SDMMC2,
371 	PMUX_FUNC_SDMMC3,
372 	PMUX_FUNC_SDMMC4,
373 	PMUX_FUNC_SFLASH,
374 	PMUX_FUNC_SPDIF,
375 	PMUX_FUNC_SPI1,
376 	PMUX_FUNC_SPI2,
377 	PMUX_FUNC_SPI2_ALT,
378 	PMUX_FUNC_SPI3,
379 	PMUX_FUNC_SPI4,
380 	PMUX_FUNC_TRACE,
381 	PMUX_FUNC_TWC,
382 	PMUX_FUNC_UARTA,
383 	PMUX_FUNC_UARTB,
384 	PMUX_FUNC_UARTC,
385 	PMUX_FUNC_UARTD,
386 	PMUX_FUNC_UARTE,
387 	PMUX_FUNC_ULPI,
388 	PMUX_FUNC_VI,
389 	PMUX_FUNC_VI_SENSOR_CLK,
390 	PMUX_FUNC_XIO,
391 	PMUX_FUNC_BLINK,
392 	PMUX_FUNC_CEC,
393 	PMUX_FUNC_CLK12,
394 	PMUX_FUNC_DAP,
395 	PMUX_FUNC_DAPSDMMC2,
396 	PMUX_FUNC_DDR,
397 	PMUX_FUNC_DEV3,
398 	PMUX_FUNC_DTV,
399 	PMUX_FUNC_VI_ALT1,
400 	PMUX_FUNC_VI_ALT2,
401 	PMUX_FUNC_VI_ALT3,
402 	PMUX_FUNC_EMC_DLL,
403 	PMUX_FUNC_EXTPERIPH1,
404 	PMUX_FUNC_EXTPERIPH2,
405 	PMUX_FUNC_EXTPERIPH3,
406 	PMUX_FUNC_GMI_ALT,
407 	PMUX_FUNC_HDA,
408 	PMUX_FUNC_HSI,
409 	PMUX_FUNC_I2C4,
410 	PMUX_FUNC_I2C5,
411 	PMUX_FUNC_I2CPWR,
412 	PMUX_FUNC_I2S0,
413 	PMUX_FUNC_I2S1,
414 	PMUX_FUNC_I2S2,
415 	PMUX_FUNC_I2S3,
416 	PMUX_FUNC_I2S4,
417 	PMUX_FUNC_NAND_ALT,
418 	PMUX_FUNC_POPSDIO4,
419 	PMUX_FUNC_POPSDMMC4,
420 	PMUX_FUNC_PWM0,
421 	PMUX_FUNC_PWM1,
422 	PMUX_FUNC_PWM2,
423 	PMUX_FUNC_PWM3,
424 	PMUX_FUNC_SATA,
425 	PMUX_FUNC_SPI5,
426 	PMUX_FUNC_SPI6,
427 	PMUX_FUNC_SYSCLK,
428 	PMUX_FUNC_VGP1,
429 	PMUX_FUNC_VGP2,
430 	PMUX_FUNC_VGP3,
431 	PMUX_FUNC_VGP4,
432 	PMUX_FUNC_VGP5,
433 	PMUX_FUNC_VGP6,
434 	PMUX_FUNC_CLK_12M_OUT,
435 	PMUX_FUNC_HDCP,
436 	PMUX_FUNC_TEST,
437 	PMUX_FUNC_CORE_PWR_REQ,
438 	PMUX_FUNC_CPU_PWR_REQ,
439 	PMUX_FUNC_PWR_INT_N,
440 	PMUX_FUNC_CLK_32K_IN,
441 	PMUX_FUNC_SAFE,
442 
443 	PMUX_FUNC_MAX,
444 
445 	PMUX_FUNC_RSVD1 = 0x8000,
446 	PMUX_FUNC_RSVD2 = 0x8001,
447 	PMUX_FUNC_RSVD3 = 0x8002,
448 	PMUX_FUNC_RSVD4 = 0x8003,
449 };
450 
451 /* return 1 if a pmux_func is in range */
452 #define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
453 	|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
454 
455 /* return 1 if a pingrp is in range */
456 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
457 
458 /* The pullup/pulldown state of a pin group */
459 enum pmux_pull {
460 	PMUX_PULL_NORMAL = 0,
461 	PMUX_PULL_DOWN,
462 	PMUX_PULL_UP,
463 };
464 /* return 1 if a pin_pupd_is in range */
465 #define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
466 				((pupd) <= PMUX_PULL_UP))
467 
468 /* Defines whether a pin group is tristated or in normal operation */
469 enum pmux_tristate {
470 	PMUX_TRI_NORMAL = 0,
471 	PMUX_TRI_TRISTATE = 1,
472 };
473 /* return 1 if a pin_tristate_is in range */
474 #define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
475 				&& ((tristate) <= PMUX_TRI_TRISTATE))
476 
477 enum pmux_pin_io {
478 	PMUX_PIN_OUTPUT = 0,
479 	PMUX_PIN_INPUT = 1,
480 };
481 /* return 1 if a pin_io_is in range */
482 #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
483 				((io) <= PMUX_PIN_INPUT))
484 
485 enum pmux_pin_lock {
486 	PMUX_PIN_LOCK_DEFAULT = 0,
487 	PMUX_PIN_LOCK_DISABLE,
488 	PMUX_PIN_LOCK_ENABLE,
489 };
490 /* return 1 if a pin_lock is in range */
491 #define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
492 				((lock) <= PMUX_PIN_LOCK_ENABLE))
493 
494 enum pmux_pin_od {
495 	PMUX_PIN_OD_DEFAULT = 0,
496 	PMUX_PIN_OD_DISABLE,
497 	PMUX_PIN_OD_ENABLE,
498 };
499 /* return 1 if a pin_od is in range */
500 #define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
501 				((od) <= PMUX_PIN_OD_ENABLE))
502 
503 enum pmux_pin_ioreset {
504 	PMUX_PIN_IO_RESET_DEFAULT = 0,
505 	PMUX_PIN_IO_RESET_DISABLE,
506 	PMUX_PIN_IO_RESET_ENABLE,
507 };
508 /* return 1 if a pin_ioreset_is in range */
509 #define pmux_pin_ioreset_isvalid(ioreset) \
510 				(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
511 				((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
512 
513 /* Available power domains used by pin groups */
514 enum pmux_vddio {
515 	PMUX_VDDIO_BB = 0,
516 	PMUX_VDDIO_LCD,
517 	PMUX_VDDIO_VI,
518 	PMUX_VDDIO_UART,
519 	PMUX_VDDIO_DDR,
520 	PMUX_VDDIO_NAND,
521 	PMUX_VDDIO_SYS,
522 	PMUX_VDDIO_AUDIO,
523 	PMUX_VDDIO_SD,
524 	PMUX_VDDIO_CAM,
525 	PMUX_VDDIO_GMI,
526 	PMUX_VDDIO_PEXCTL,
527 	PMUX_VDDIO_SDMMC1,
528 	PMUX_VDDIO_SDMMC3,
529 	PMUX_VDDIO_SDMMC4,
530 
531 	PMUX_VDDIO_NONE
532 };
533 
534 /* t30 pin drive group and pin mux registers */
535 #define PDRIVE_PINGROUP_OFFSET	(0x868 >> 2)
536 #define PMUX_OFFSET	((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
537 				PDRIVE_PINGROUP_COUNT)
538 struct pmux_tri_ctlr {
539 	uint pmt_reserved0;		/* ABP_MISC_PP_ reserved offset 00 */
540 	uint pmt_reserved1;		/* ABP_MISC_PP_ reserved offset 04 */
541 	uint pmt_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 08   */
542 	uint pmt_reserved2;		/* ABP_MISC_PP_ reserved offset 0C */
543 	uint pmt_reserved3;		/* ABP_MISC_PP_ reserved offset 10 */
544 	uint pmt_reserved4[4];		/* _TRI_STATE_REG_A/B/C/D in t20 */
545 	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24        */
546 
547 	uint pmt_reserved[528];		/* ABP_MISC_PP_ reserved offs 28-864 */
548 
549 	uint pmt_drive[PDRIVE_PINGROUP_COUNT];	/* pin drive grps offs 868 */
550 	uint pmt_reserved5[PMUX_OFFSET];
551 	uint pmt_ctl[PINGRP_COUNT];	/* mux/pupd/tri regs, offset 0x3000 */
552 };
553 
554 /*
555  * This defines the configuration for a pin, including the function assigned,
556  * pull up/down settings and tristate settings. Having set up one of these
557  * you can call pinmux_config_pingroup() to configure a pin in one step. Also
558  * available is pinmux_config_table() to configure a list of pins.
559  */
560 struct pingroup_config {
561 	enum pmux_pingrp pingroup;	/* pin group PINGRP_...             */
562 	enum pmux_func func;		/* function to assign FUNC_...      */
563 	enum pmux_pull pull;		/* pull up/down/normal PMUX_PULL_...*/
564 	enum pmux_tristate tristate;	/* tristate or normal PMUX_TRI_...  */
565 	enum pmux_pin_io io;		/* input or output PMUX_PIN_...  */
566 	enum pmux_pin_lock lock;	/* lock enable/disable PMUX_PIN...  */
567 	enum pmux_pin_od od;		/* open-drain or push-pull driver  */
568 	enum pmux_pin_ioreset ioreset;	/* input/output reset PMUX_PIN...  */
569 };
570 
571 /* Set a pin group to tristate */
572 void pinmux_tristate_enable(enum pmux_pingrp pin);
573 
574 /* Set a pin group to normal (non tristate) */
575 void pinmux_tristate_disable(enum pmux_pingrp pin);
576 
577 /* Set the pull up/down feature for a pin group */
578 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
579 
580 /* Set the mux function for a pin group */
581 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
582 
583 /* Set the complete configuration for a pin group */
584 void pinmux_config_pingroup(struct pingroup_config *config);
585 
586 /* Set a pin group to tristate or normal */
587 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
588 
589 /* Set a pin group as input or output */
590 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
591 
592 /**
593  * Configure a list of pin groups
594  *
595  * @param config	List of config items
596  * @param len		Number of config items in list
597  */
598 void pinmux_config_table(struct pingroup_config *config, int len);
599 
600 /* Set a group of pins from a table */
601 void pinmux_init(void);
602 
603 #endif	/* _TEGRA30_PINMUX_H_ */
604