1 /* 2 * (C) Copyright 2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA30_MC_H_ 9 #define _TEGRA30_MC_H_ 10 11 /** 12 * Defines the memory controller registers we need/care about 13 */ 14 struct mc_ctlr { 15 u32 reserved0[4]; /* offset 0x00 - 0x0C */ 16 u32 mc_smmu_config; /* offset 0x10 */ 17 u32 mc_smmu_tlb_config; /* offset 0x14 */ 18 u32 mc_smmu_ptc_config; /* offset 0x18 */ 19 u32 mc_smmu_ptb_asid; /* offset 0x1C */ 20 u32 mc_smmu_ptb_data; /* offset 0x20 */ 21 u32 reserved1[3]; /* offset 0x24 - 0x2C */ 22 u32 mc_smmu_tlb_flush; /* offset 0x30 */ 23 u32 mc_smmu_ptc_flush; /* offset 0x34 */ 24 u32 mc_smmu_asid_security; /* offset 0x38 */ 25 u32 reserved2[5]; /* offset 0x3C - 0x4C */ 26 u32 mc_emem_cfg; /* offset 0x50 */ 27 u32 mc_emem_adr_cfg; /* offset 0x54 */ 28 u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ 29 u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ 30 u32 reserved3[12]; /* offset 0x60 - 0x8C */ 31 u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ 32 u32 reserved4[338]; /* offset 0x100 - 0x644 */ 33 u32 mc_video_protect_bom; /* offset 0x648 */ 34 u32 mc_video_protect_size_mb; /* offset 0x64c */ 35 u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ 36 }; 37 38 #endif /* _TEGRA30_MC_H_ */ 39