1 /*
2  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #ifndef _TEGRA30_GP_PADCTRL_H_
18 #define _TEGRA30_GP_PADCTRL_H_
19 
20 #include <asm/arch-tegra/gp_padctrl.h>
21 
22 /* APB_MISC_GP and padctrl registers */
23 struct apb_misc_gp_ctlr {
24 	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
25 	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
26 	u32	reserved0[22];	/* 0x08 - 0x5C: */
27 	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
28 	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
29 	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
30 	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
31 	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
32 	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
33 	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
34 	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
35 	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
36 	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
37 	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
38 	u32	csuscfg;	/* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
39 	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
40 	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
41 	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
42 	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
43 	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
44 	u32	lcdcfg1;	/* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
45 	u32	lcdcfg2;	/* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
46 	u32	sdio2cfg;	/* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
47 	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
48 	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
49 	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
50 	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
51 	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
52 	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
53 	u32	vicfg1;		/* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
54 	u32	vivttgen;	/* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
55 	u32	reserved1[7];	/* 0xD0-0xE8: */
56 	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
57 };
58 
59 /* SDMMC1/3 settings from section 24.6 of T30 TRM */
60 #define SDIOCFG_DRVUP_SLWF	1
61 #define SDIOCFG_DRVDN_SLWR	1
62 #define SDIOCFG_DRVUP		0x2E
63 #define SDIOCFG_DRVDN		0x2A
64 
65 #endif	/* _TEGRA30_GP_PADCTRL_H_ */
66