1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2dc89ad14STom Warren /* 3dc89ad14STom Warren * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 4dc89ad14STom Warren */ 5dc89ad14STom Warren 6dc89ad14STom Warren /* Tegra30 high-level function multiplexing */ 7dc89ad14STom Warren 8dc89ad14STom Warren #ifndef _TEGRA30_FUNCMUX_H_ 9dc89ad14STom Warren #define _TEGRA30_FUNCMUX_H_ 10dc89ad14STom Warren 11dc89ad14STom Warren #include <asm/arch-tegra/funcmux.h> 12dc89ad14STom Warren 13dc89ad14STom Warren /* Configs supported by the func mux */ 14dc89ad14STom Warren enum { 15dc89ad14STom Warren FUNCMUX_DEFAULT = 0, /* default config */ 16dc89ad14STom Warren 17dc89ad14STom Warren /* UART configs */ 18dc89ad14STom Warren FUNCMUX_UART1_ULPI = 0, 19dc89ad14STom Warren }; 20dc89ad14STom Warren #endif /* _TEGRA30_FUNCMUX_H_ */ 21