1 /*
2  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 /* Tegra30 clock PLL tables */
18 
19 #ifndef _TEGRA30_CLOCK_TABLES_H_
20 #define _TEGRA30_CLOCK_TABLES_H_
21 
22 /* The PLLs supported by the hardware */
23 enum clock_id {
24 	CLOCK_ID_FIRST,
25 	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
26 	CLOCK_ID_MEMORY,
27 	CLOCK_ID_PERIPH,
28 	CLOCK_ID_AUDIO,
29 	CLOCK_ID_USB,
30 	CLOCK_ID_DISPLAY,
31 
32 	/* now the simple ones */
33 	CLOCK_ID_FIRST_SIMPLE,
34 	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
35 	CLOCK_ID_EPCI,
36 	CLOCK_ID_SFROM32KHZ,
37 
38 	/* These are the base clocks (inputs to the Tegra SOC) */
39 	CLOCK_ID_32KHZ,
40 	CLOCK_ID_OSC,
41 	CLOCK_ID_CLK_M,
42 
43 	CLOCK_ID_COUNT,	/* number of PLLs */
44 	CLOCK_ID_DISPLAY2,	/* Tegra3, placeholder */
45 	CLOCK_ID_NONE = -1,
46 };
47 
48 /* The clocks supported by the hardware */
49 enum periph_id {
50 	PERIPH_ID_FIRST,
51 
52 	/* Low word: 31:0 */
53 	PERIPH_ID_CPU = PERIPH_ID_FIRST,
54 	PERIPH_ID_COP,
55 	PERIPH_ID_TRIGSYS,
56 	PERIPH_ID_RESERVED3,
57 	PERIPH_ID_RESERVED4,
58 	PERIPH_ID_TMR,
59 	PERIPH_ID_UART1,
60 	PERIPH_ID_UART2,
61 
62 	/* 8 */
63 	PERIPH_ID_GPIO,
64 	PERIPH_ID_SDMMC2,
65 	PERIPH_ID_SPDIF,
66 	PERIPH_ID_I2S1,
67 	PERIPH_ID_I2C1,
68 	PERIPH_ID_NDFLASH,
69 	PERIPH_ID_SDMMC1,
70 	PERIPH_ID_SDMMC4,
71 
72 	/* 16 */
73 	PERIPH_ID_RESERVED16,
74 	PERIPH_ID_PWM,
75 	PERIPH_ID_I2S2,
76 	PERIPH_ID_EPP,
77 	PERIPH_ID_VI,
78 	PERIPH_ID_2D,
79 	PERIPH_ID_USBD,
80 	PERIPH_ID_ISP,
81 
82 	/* 24 */
83 	PERIPH_ID_3D,
84 	PERIPH_ID_RESERVED24,
85 	PERIPH_ID_DISP2,
86 	PERIPH_ID_DISP1,
87 	PERIPH_ID_HOST1X,
88 	PERIPH_ID_VCP,
89 	PERIPH_ID_I2S0,
90 	PERIPH_ID_CACHE2,
91 
92 	/* Middle word: 63:32 */
93 	PERIPH_ID_MEM,
94 	PERIPH_ID_AHBDMA,
95 	PERIPH_ID_APBDMA,
96 	PERIPH_ID_RESERVED35,
97 	PERIPH_ID_KBC,
98 	PERIPH_ID_STAT_MON,
99 	PERIPH_ID_PMC,
100 	PERIPH_ID_FUSE,
101 
102 	/* 40 */
103 	PERIPH_ID_KFUSE,
104 	PERIPH_ID_SBC1,
105 	PERIPH_ID_SNOR,
106 	PERIPH_ID_RESERVED43,
107 	PERIPH_ID_SBC2,
108 	PERIPH_ID_RESERVED45,
109 	PERIPH_ID_SBC3,
110 	PERIPH_ID_DVC_I2C,
111 
112 	/* 48 */
113 	PERIPH_ID_DSI,
114 	PERIPH_ID_TVO,
115 	PERIPH_ID_MIPI,
116 	PERIPH_ID_HDMI,
117 	PERIPH_ID_CSI,
118 	PERIPH_ID_TVDAC,
119 	PERIPH_ID_I2C2,
120 	PERIPH_ID_UART3,
121 
122 	/* 56 */
123 	PERIPH_ID_RESERVED56,
124 	PERIPH_ID_EMC,
125 	PERIPH_ID_USB2,
126 	PERIPH_ID_USB3,
127 	PERIPH_ID_MPE,
128 	PERIPH_ID_VDE,
129 	PERIPH_ID_BSEA,
130 	PERIPH_ID_BSEV,
131 
132 	/* Upper word 95:64 */
133 	PERIPH_ID_SPEEDO,
134 	PERIPH_ID_UART4,
135 	PERIPH_ID_UART5,
136 	PERIPH_ID_I2C3,
137 	PERIPH_ID_SBC4,
138 	PERIPH_ID_SDMMC3,
139 	PERIPH_ID_PCIE,
140 	PERIPH_ID_OWR,
141 
142 	/* 72 */
143 	PERIPH_ID_AFI,
144 	PERIPH_ID_CORESIGHT,
145 	PERIPH_ID_PCIEXCLK,
146 	PERIPH_ID_AVPUCQ,
147 	PERIPH_ID_RESERVED76,
148 	PERIPH_ID_RESERVED77,
149 	PERIPH_ID_RESERVED78,
150 	PERIPH_ID_DTV,
151 
152 	/* 80 */
153 	PERIPH_ID_NANDSPEED,
154 	PERIPH_ID_I2CSLOW,
155 	PERIPH_ID_DSIB,
156 	PERIPH_ID_RESERVED83,
157 	PERIPH_ID_IRAMA,
158 	PERIPH_ID_IRAMB,
159 	PERIPH_ID_IRAMC,
160 	PERIPH_ID_IRAMD,
161 
162 	/* 88 */
163 	PERIPH_ID_CRAM2,
164 	PERIPH_ID_RESERVED89,
165 	PERIPH_ID_MDOUBLER,
166 	PERIPH_ID_RESERVED91,
167 	PERIPH_ID_SUSOUT,
168 	PERIPH_ID_RESERVED93,
169 	PERIPH_ID_RESERVED94,
170 	PERIPH_ID_RESERVED95,
171 
172 	PERIPH_ID_VW_FIRST,
173 	/* V word: 31:0 */
174 	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
175 	PERIPH_ID_CPULP,
176 	PERIPH_ID_3D2,
177 	PERIPH_ID_MSELECT,
178 	PERIPH_ID_TSENSOR,
179 	PERIPH_ID_I2S3,
180 	PERIPH_ID_I2S4,
181 	PERIPH_ID_I2C4,
182 
183 	/* 08 */
184 	PERIPH_ID_SBC5,
185 	PERIPH_ID_SBC6,
186 	PERIPH_ID_AUDIO,
187 	PERIPH_ID_APBIF,
188 	PERIPH_ID_DAM0,
189 	PERIPH_ID_DAM1,
190 	PERIPH_ID_DAM2,
191 	PERIPH_ID_HDA2CODEC2X,
192 
193 	/* 16 */
194 	PERIPH_ID_ATOMICS,
195 	PERIPH_ID_EX_RESERVED17,
196 	PERIPH_ID_EX_RESERVED18,
197 	PERIPH_ID_EX_RESERVED19,
198 	PERIPH_ID_EX_RESERVED20,
199 	PERIPH_ID_EX_RESERVED21,
200 	PERIPH_ID_EX_RESERVED22,
201 	PERIPH_ID_ACTMON,
202 
203 	/* 24 */
204 	PERIPH_ID_EX_RESERVED24,
205 	PERIPH_ID_EX_RESERVED25,
206 	PERIPH_ID_EX_RESERVED26,
207 	PERIPH_ID_EX_RESERVED27,
208 	PERIPH_ID_SATA,
209 	PERIPH_ID_HDA,
210 	PERIPH_ID_EX_RESERVED30,
211 	PERIPH_ID_EX_RESERVED31,
212 
213 	/* W word: 31:0 */
214 	PERIPH_ID_HDA2HDMICODEC,
215 	PERIPH_ID_SATACOLD,
216 	PERIPH_ID_RESERVED0_PCIERX0,
217 	PERIPH_ID_RESERVED1_PCIERX1,
218 	PERIPH_ID_RESERVED2_PCIERX2,
219 	PERIPH_ID_RESERVED3_PCIERX3,
220 	PERIPH_ID_RESERVED4_PCIERX4,
221 	PERIPH_ID_RESERVED5_PCIERX5,
222 
223 	/* 40 */
224 	PERIPH_ID_CEC,
225 	PERIPH_ID_RESERVED6_PCIE2,
226 	PERIPH_ID_RESERVED7_EMC,
227 	PERIPH_ID_RESERVED8_HDMI,
228 	PERIPH_ID_RESERVED9_SATA,
229 	PERIPH_ID_RESERVED10_MIPI,
230 	PERIPH_ID_EX_RESERVED46,
231 	PERIPH_ID_EX_RESERVED47,
232 
233 	PERIPH_ID_COUNT,
234 	PERIPH_ID_NONE = -1,
235 };
236 
237 enum pll_out_id {
238 	PLL_OUT1,
239 	PLL_OUT2,
240 	PLL_OUT3,
241 	PLL_OUT4
242 };
243 
244 /*
245  * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
246  * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
247  * confusion bewteen PERIPH_ID_... and PERIPHC_...
248  *
249  * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
250  * confusing.
251  */
252 enum periphc_internal_id {
253 	/* 0x00 */
254 	PERIPHC_I2S1,
255 	PERIPHC_I2S2,
256 	PERIPHC_SPDIF_OUT,
257 	PERIPHC_SPDIF_IN,
258 	PERIPHC_PWM,
259 	PERIPHC_05h,
260 	PERIPHC_SBC2,
261 	PERIPHC_SBC3,
262 
263 	/* 0x08 */
264 	PERIPHC_08h,
265 	PERIPHC_I2C1,
266 	PERIPHC_DVC_I2C,
267 	PERIPHC_0bh,
268 	PERIPHC_0ch,
269 	PERIPHC_SBC1,
270 	PERIPHC_DISP1,
271 	PERIPHC_DISP2,
272 
273 	/* 0x10 */
274 	PERIPHC_CVE,
275 	PERIPHC_11h,
276 	PERIPHC_VI,
277 	PERIPHC_13h,
278 	PERIPHC_SDMMC1,
279 	PERIPHC_SDMMC2,
280 	PERIPHC_G3D,
281 	PERIPHC_G2D,
282 
283 	/* 0x18 */
284 	PERIPHC_NDFLASH,
285 	PERIPHC_SDMMC4,
286 	PERIPHC_VFIR,
287 	PERIPHC_EPP,
288 	PERIPHC_MPE,
289 	PERIPHC_MIPI,
290 	PERIPHC_UART1,
291 	PERIPHC_UART2,
292 
293 	/* 0x20 */
294 	PERIPHC_HOST1X,
295 	PERIPHC_21h,
296 	PERIPHC_TVO,
297 	PERIPHC_HDMI,
298 	PERIPHC_24h,
299 	PERIPHC_TVDAC,
300 	PERIPHC_I2C2,
301 	PERIPHC_EMC,
302 
303 	/* 0x28 */
304 	PERIPHC_UART3,
305 	PERIPHC_29h,
306 	PERIPHC_VI_SENSOR,
307 	PERIPHC_2bh,
308 	PERIPHC_2ch,
309 	PERIPHC_SBC4,
310 	PERIPHC_I2C3,
311 	PERIPHC_SDMMC3,
312 
313 	/* 0x30 */
314 	PERIPHC_UART4,
315 	PERIPHC_UART5,
316 	PERIPHC_VDE,
317 	PERIPHC_OWR,
318 	PERIPHC_NOR,
319 	PERIPHC_CSITE,
320 	PERIPHC_I2S0,
321 	PERIPHC_37h,
322 
323 	PERIPHC_VW_FIRST,
324 	/* 0x38 */
325 	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
326 	PERIPHC_MSELECT,
327 	PERIPHC_TSENSOR,
328 	PERIPHC_I2S3,
329 	PERIPHC_I2S4,
330 	PERIPHC_I2C4,
331 	PERIPHC_SBC5,
332 	PERIPHC_SBC6,
333 
334 	/* 0x40 */
335 	PERIPHC_AUDIO,
336 	PERIPHC_41h,
337 	PERIPHC_DAM0,
338 	PERIPHC_DAM1,
339 	PERIPHC_DAM2,
340 	PERIPHC_HDA2CODEC2X,
341 	PERIPHC_ACTMON,
342 	PERIPHC_EXTPERIPH1,
343 
344 	/* 0x48 */
345 	PERIPHC_EXTPERIPH2,
346 	PERIPHC_EXTPERIPH3,
347 	PERIPHC_NANDSPEED,
348 	PERIPHC_I2CSLOW,
349 	PERIPHC_SYS,
350 	PERIPHC_SPEEDO,
351 	PERIPHC_4eh,
352 	PERIPHC_4fh,
353 
354 	/* 0x50 */
355 	PERIPHC_50h,
356 	PERIPHC_51h,
357 	PERIPHC_52h,
358 	PERIPHC_53h,
359 	PERIPHC_SATAOOB,
360 	PERIPHC_SATA,
361 	PERIPHC_HDA,
362 
363 	PERIPHC_COUNT,
364 
365 	PERIPHC_NONE = -1,
366 };
367 
368 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
369 #define PERIPH_REG(id) \
370 	(id < PERIPH_ID_VW_FIRST) ? \
371 		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
372 
373 /* Mask value for a clock (within PERIPH_REG(id)) */
374 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
375 
376 /* return 1 if a PLL ID is in range */
377 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
378 
379 /* return 1 if a peripheral ID is in range */
380 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
381 		(id) < PERIPH_ID_COUNT)
382 
383 #endif	/* _TEGRA30_CLOCK_TABLES_H_ */
384