1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26c43f6c8STom Warren /* 36c43f6c8STom Warren * (C) Copyright 2013-2015 46c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 56c43f6c8STom Warren */ 66c43f6c8STom Warren 76c43f6c8STom Warren #ifndef _TEGRA210_TEGRA_H_ 86c43f6c8STom Warren #define _TEGRA210_TEGRA_H_ 96c43f6c8STom Warren 106c43f6c8STom Warren #define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ 116c43f6c8STom Warren #define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ 126c43f6c8STom Warren #define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ 136c43f6c8STom Warren #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 146c43f6c8STom Warren #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ 156c43f6c8STom Warren #define NV_PA_SDRAM_BASE 0x80000000 166c43f6c8STom Warren 176c43f6c8STom Warren #include <asm/arch-tegra/tegra.h> 186c43f6c8STom Warren 196c43f6c8STom Warren #define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ 206c43f6c8STom Warren 216c43f6c8STom Warren #undef NVBOOTINFOTABLE_BCTSIZE 226c43f6c8STom Warren #undef NVBOOTINFOTABLE_BCTPTR 236c43f6c8STom Warren #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 246c43f6c8STom Warren #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 256c43f6c8STom Warren 266c43f6c8STom Warren #define MAX_NUM_CPU 4 276c43f6c8STom Warren #define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) 286c43f6c8STom Warren 296c43f6c8STom Warren #define TEGRA_USB1_BASE 0x7D000000 306c43f6c8STom Warren 316c43f6c8STom Warren #endif /* _TEGRA210_TEGRA_H_ */ 32