1*6c43f6c8STom Warren /* 2*6c43f6c8STom Warren * (C) Copyright 2013-2015 3*6c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 4*6c43f6c8STom Warren * 5*6c43f6c8STom Warren * SPDX-License-Identifier: GPL-2.0+ 6*6c43f6c8STom Warren */ 7*6c43f6c8STom Warren 8*6c43f6c8STom Warren #ifndef _TEGRA210_TEGRA_H_ 9*6c43f6c8STom Warren #define _TEGRA210_TEGRA_H_ 10*6c43f6c8STom Warren 11*6c43f6c8STom Warren #define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ 12*6c43f6c8STom Warren #define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ 13*6c43f6c8STom Warren #define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ 14*6c43f6c8STom Warren #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 15*6c43f6c8STom Warren #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ 16*6c43f6c8STom Warren #define NV_PA_SDRAM_BASE 0x80000000 17*6c43f6c8STom Warren 18*6c43f6c8STom Warren #include <asm/arch-tegra/tegra.h> 19*6c43f6c8STom Warren 20*6c43f6c8STom Warren #define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ 21*6c43f6c8STom Warren 22*6c43f6c8STom Warren #undef NVBOOTINFOTABLE_BCTSIZE 23*6c43f6c8STom Warren #undef NVBOOTINFOTABLE_BCTPTR 24*6c43f6c8STom Warren #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 25*6c43f6c8STom Warren #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 26*6c43f6c8STom Warren 27*6c43f6c8STom Warren #define MAX_NUM_CPU 4 28*6c43f6c8STom Warren #define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) 29*6c43f6c8STom Warren 30*6c43f6c8STom Warren #define TEGRA_USB1_BASE 0x7D000000 31*6c43f6c8STom Warren 32*6c43f6c8STom Warren #endif /* _TEGRA210_TEGRA_H_ */ 33